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Patent # Description
US-9,571,141 Wireless communication device and method of operating the same
A calibrator to process an output signal of an analog digital converter in a wireless communication device, the calibrator comprising a level filter to remove...
US-9,571,140 Space-time coding for zero-tail spread OFDM system in a wireless network
An example technique may include controlling receiving a first block of time domain symbols and a second block of time domain symbols, converting the blocks of...
US-9,571,139 Reference circuits for biasing radio frequency electronics
Reference circuits for biasing radio frequency electronics are provided herein. In certain implementations, a gallium arsenide die includes a power amplifier...
US-9,571,138 Transmission device and noise removal method
A base station device includes: a converting unit that converts a transmission signal with a multi-bit quantization bit rate to a signal with a quantization bit...
US-9,571,137 Single tone RF signal generator
A single tone RF signal generator and a method of generating a single tone RF signal. The single tone RF signal generator includes an output and a power...
US-9,571,136 Apparatus for transmitting and receiving signals in radio frequency system
An apparatus for receiving signals in a radio frequency system includes a low noise amplifier that amplifies and filters a signal received from an antenna; a...
US-9,571,135 Adjusting power amplifier stimuli based on output signals
Compensation for one or more effects of impedance mismatch between a power amplifier (PA) and at least one filter is discussed. One example system that...
US-9,571,134 Transmit noise reducer
A transmit drive circuit with high signal to noise and frequency agility. In one embodiment, a transmit circuit includes a digital to analog converter, an...
US-9,571,133 Duplexer
A duplexer having good insulation, small geometric dimensions and good decoupling of the transmit signal path from an antenna which may have poor matching is...
US-9,571,132 Radio transmitter system and method
A radio transmitter system includes: a transmitter for deriving a carrier frequency modulated by an input; an electrically short antenna system, and a matching...
US-9,571,131 Signal generating method and signal generating device
A transmission method of simultaneously transmitting a first modulated signal and a second modulated signal at a common frequency performs precoding on both...
US-9,571,130 Method and apparatus for encoding and decoding in electronic device
A method and an apparatus for encoding and decoding in an electronic device are provided. In a decoding method, at least one parity symbol is received. A Cauchy...
US-9,571,129 Method and arrangement for decoding a signal encoded by a tail-biting code
A method of decoding a signal that has been encoded by a tail-biting code based on at least one encoding parameter is disclosed. The at least one encoding...
US-9,571,128 Dynamic adjustment of data protection schemes in flash storage systems based on temperature, power off duration...
A data retention methodology for use in electrically rewritable nonvolatile storage systems is disclosed. The methodology collects characteristic data of the...
US-9,571,127 Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for...
The present invention provides a method of transmitting broadcast signals, the method including, encoding service data, building at least one signal frame by...
US-9,571,126 Convolution-encoded hyper-speed channel with robust trellis error-correction
A method, system, and computer program product for performing robust, parallel data transfer by a processor device. Data is segmented into k-bit segments, where...
US-9,571,125 Systems and methods of vector-DMA cache-XOR for MPCC erasure coding
System and method embodiments are provided for managing storage systems. In an embodiment, a network component for managing data storage includes a storage...
US-9,571,124 Method for generating forward error correction packet in multimedia system and method and apparatus for...
A method and apparatus for transmitting a Forward Error Correction (FEC) packet block including a plurality of FEC packets in a multimedia system are provided....
US-9,571,123 Data compression systems and methods
Data compression using a combination of content independent data compression and content dependent data compression. In one aspect, a system for compressing...
US-9,571,122 Enhanced data compression for sparse multidimensional ordered series data
Disclosed are methods and systems for significantly compressing sparse multidimensional ordered series data comprised of indexed data sets, wherein each data...
US-9,571,121 Electrochemical sensing module
A sensing circuit for an electrochemical sensor includes a digital-to-analog converter (DAC), an operational amplifier, an instrumentation amplifier, and an...
US-9,571,120 Digital to analog converter circuits, apparatus and method for generating a high frequency transmission signal...
A digital to analog converter circuit includes a plurality of digital to analog converter cells. The digital to analog converter circuit further includes a...
US-9,571,119 Defeat of aliasing by incremental sampling
A method includes generating a sampling signal having a non-uniform sampling interval and sampling a received signal with an analog-to-digital converter (ADC)...
US-9,571,118 Pre-charge buffer for analog-to-digital converter
A pre-charge buffer for sampling input signals and generating a sampled output signal includes a coarse sampling circuit, a fine sampling circuit, and a sample...
US-9,571,117 Digital-analog conversion apparatus and method
An apparatus and a method for digital-analog conversion are provided. The apparatus includes a first cell matrix for outputting a current of a signal...
US-9,571,116 Circuit and method of adaptive filtering digital calibration of ADC
An adaptive filtering digital calibration circuit of ADC, which includes a control module, a fixed-point adder, and a fixed-point multiplier; the control module...
US-9,571,115 Analog to digital converter with high precision offset calibrated integrating comparators
An analog-to-digital converter includes a plurality of slave sampler multiplexers responsive to outputs of a master sampler that receives analog signals and...
US-9,571,114 SAR ADC performance optimization with dynamic bit trial settings
An analog-to-digital converter (ADC) circuit comprises a digital-to-analog (DAC) circuit including at least N+n weighted circuit components, wherein N and n are...
US-9,571,113 Integral A/D converter and CMOS image sensor
The integral type Analog/Digital (AD) converter includes: a comparator configured to compare a reference voltage of a ramp waveform with an input voltage and...
US-9,571,112 Stacked synthesizer for wide local oscillator generation using a dynamic divider
A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled...
US-9,571,111 System and method to speed up PLL lock time on subsequent calibrations via stored band values
A method and apparatus and computer program product for calibrating a Phase Lock Loop (PLL) that reduces a PLL lock time for subsequent calibrations to thereby...
US-9,571,110 Delay circuit, delay locked loop circuit including delay circuit and processor including delay locked loop circuit
A delay circuit comprises a plurality of delay buffers each including two or more serially connected delay units, each of the delay units being capable of...
US-9,571,109 Voltage controlled oscillator runaway prevention
A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third...
US-9,571,108 Multi-output phase detector
Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit...
US-9,571,107 High-order sigma delta for a divider-less digital phase-locked loop
Described herein are technologies related to an implementation of a divider-less digital phase-locked loop (DPLL) that includes a loop response matching a...
US-9,571,106 Delay locked loop circuit
A delay locked loop (DLL) circuit may include: a DLL unit suitable for generating an internal clock by delaying an external clock by a delay amount required for...
US-9,571,105 System and method for an accuracy-enhanced DLL during a measure initialization mode
A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay...
US-9,571,104 Programmable body bias power supply
Methods and apparatus permit body biasing to be controlled for transistors of a logic device. By controlling the body biasing, transistor threshold voltages can...
US-9,571,103 Lookup table and programmable logic device including lookup table
A lookup table with low power consumption is provided. The lookup table includes a memory element including a transistor and a capacitor. A drain of the...
US-9,571,102 Semiconductor device having impedance calibration function to data output buffer and semiconductor module...
Disclosed herein is a semiconductor device that includes a first transistor unit coupled to the data terminal, and a plurality of second transistor units...
US-9,571,101 Semiconductor device
According to one embodiment, a semiconductor device includes: a first circuit including a first transistor, a second transistor, the first and second...
US-9,571,100 Clock buffers with pulse drive capability for power efficiency
A clock driver is provided. The clock driver includes a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving...
US-9,571,099 Electronic device comprising multiplexer and driving method thereof
A method for driving a semiconductor device capable of reducing an area of a multiplexer and reducing its power consumption is provided. In a method for...
US-9,571,098 Signal receiving circuits including termination resistance having adjustable resistance value, operating...
A receiving circuit includes a termination resistance circuit and a resistance adjustment circuit. The termination resistance circuit is configured to receive a...
US-9,571,097 Touch screen and display device
The present invention provides a touch screen and a display device with better touch effect. The touch screen includes: a first substrate, a plurality of first...
US-9,571,096 Touch panel based switch
A touch panel-based switch includes a control circuit layer, a sensing layer, a dielectric layer, and a touch operation layer, stacked in the order. The sensing...
US-9,571,095 Touch device with curved surface
A curved touch device is provided in the present invention including a back cover and a touch panel corresponding to the back cover, where at least one edge...
US-9,571,094 Switch circuit
To provide a switch circuit which is capable of reliably controlling transmission of a voltage from GND to VDD to an internal circuit or shut-off thereof even...
US-9,571,093 Half bridge driver circuits
GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power...
US-9,571,092 Cascaded high voltage switch architecture
Devices and circuits for high voltage switch (HVS) configurations. HVS may pass high voltage without suffering voltage drops. HVS may also guarantee safe...
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