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Methods of forming transistor structures including forming channel
material after formation processes to...
Methods for fabricating transistor structures are provided, the methods including: forming a fin structure with an upper fin portion and a lower fin portion,...
Dislocation stress memorization technique for FinFET device
A method for performing a stress memorization technique (SMT) a FinFET and a FinFET having memorized stress effects including multi-planar dislocations are...
Fabrication methods facilitating integration of different device
Circuit fabrication methods are provided which include, for example: providing one or more gate structures disposed over a substrate structure, the substrate...
Field effect transistor devices with buried well protection regions
A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first...
Semiconductor structure and manufacturing method thereof
Some embodiments of the present disclosure provide a semiconductor device including a substrate and a gate structure on the substrate. A first well region of a...
Recessing RMG metal gate stack for forming self-aligned contact
Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect...
Method of removing dummy gate dielectric layer
A method of removing a dummy gate dielectric layer is provided. Firstly a first plasma containing F is utilized to remove the dummy dielectric layer which...
Method of forming a self-aligned stack gate structure for use in a
non-volatile memory array
A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions,...
Replacement gate process for FinFET
A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an...
Semiconductor structures and methods for multi-level work function
Semiconductor devices that each include a channel region and a gate stack are disclosed. The gate stack includes a gate insulator, a pair of spaced apart first...
Gate and gate forming process
A gate forming process includes the following steps. A gate dielectric layer is formed on a substrate. A barrier layer is formed on the gate dielectric layer. A...
Semiconductor device and insulated gate bipolar transistor with source
zones formed in semiconductor mesas
A semiconductor device includes a semiconductor mesa that includes at least one body zone forming first pn junctions with source zones and a second pn junction...
Method for forming a semiconductor device having insulating parts or
layers formed via anodic oxidation
A method for forming a semiconductor device includes forming an electrical structure at a main surface of a semiconductor substrate and carrying out an anodic...
Capacitor in strain relaxed buffer
Aspects include a semiconductor structure and fabrication method. A semiconductor structure may include alternating first and second crystalline layers and a...
Recessed metal liner contact with copper fill
A method of fabricating a contact above a source or drain region of an integrated circuit includes depositing a first liner conformally in a bottom and along a...
Self-aligned gate tie-down contacts with selective etch stop liner
A method for forming a gate tie-down includes exposing an active area to form trench contact openings and forming trench contacts therein. An etch stop layer is...
Multiple layer interface formation for semiconductor structure
There is set forth herein a method of fabricating a contact interface formation. A layer of Ti metal can be deposited on a substrate and a layer of Ni metal can...
Gate stack integrated metal resistors
Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate...
Enhanced gate dielectric for a field effect device with a trenched gate
The present disclosure relates to a silicon carbide (SiC) field effect device that has a gate assembly formed in a trench. The gate assembly includes a gate...
Selective thickening of PFET dielectric
A complementary metal-oxide semiconductor (CMOS) device and a method of fabricating a CMOS device are described. The method includes forming an interfacial...
Semiconductor component and method for fabricating the same
A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate...
Source and drain process for FinFET
A FinFET includes a substrate, a fin structure, a dielectric layer, a metal gate, two spacers, a source and a drain. The fin structure is disposed on the...
Semiconductor device including a trench at least partially filled with a
conductive material in a semiconductor...
A semiconductor device includes a semiconductor substrate and a first trench extending into or through the semiconductor substrate from a first side. The first...
Field effect power transistor metalization having a comb structure with
A metalization of a field effect power transistor having lateral semiconductor layers on an insulator substrate or an intrinsically conducting or doped...
Self-aligned emitter-base bipolar junction transistor with reduced base
resistance and base-collector capacitance
Device structures and fabrication methods for a bipolar junction transistor. A first semiconductor layer is formed on a substrate containing a first terminal....
III-V compound and Germanium compound nanowire suspension with
Germanium-containing release layer
A device that includes: a substrate layer; a first set of source/drain component(s) defining an nFET (n-type field-effect transistor) region; a second set of...
Method of planarizing polysilicon gate
A method of planarizing a polysilicon gate are provided, comprising: growing a polysilicon gate layer on a substrate with trenches; depositing an oxide layer on...
Modified channel position to suppress hot carrier injection in FinFETs
Some embodiments relate to an integrated circuit (IC) including one or more finFET devices. A finFET includes a fin of semiconductor material extending upwards...
Diffused junction termination structures for silicon carbide devices
An electronic device includes a silicon carbide layer having a first conductivity type and a main junction adjacent a surface of the silicon carbide layer, and...
Graphene device including angular split gate
An electronic device can include a dielectric layer, and a graphene layer including a first surface located upon the dielectric layer. The electronic device can...
Trap rich layer for semiconductor devices
An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect...
Tilt implantation for STI formation in FinFET structures
Techniques in fabricating a fin field-effect transistor (FinFET) include providing a substrate having a fin structure and forming an isolation region having a...
Semiconductor device and manufacturing method thereof
A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure. The...
Source and drain epitaxial semiconductor material integration for high
voltage semiconductor devices
A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having...
Robust gate spacer for semiconductor devices
After formation of a gate structure and a lower dielectric spacer laterally surrounding the gate structure, a disposable material layer is deposited and...
Semiconductor chip with integrated series resistances
A semiconductor chip has a semiconductor body with a bottom side and a top side arranged distant from the bottom side in a vertical direction, an active and a...
Forming symmetrical stress liners for strained CMOS vertical nanowire
A method of forming symmetrical stress liners to maintain strain in CMOS vertical NW FETs and the resulting device are provided. Embodiments include providing a...
Replacement III-V or germanium nanowires by unilateral confined epitaxial
A lateral epitaxial growth process is employed to facilitate the fabrication of a semiconductor structure including a stack of suspended III-V or germanium...
Stacked nanowire semiconductor device
A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second...
Semiconductor nanocrystal and preparation method thereof
A semiconductor nanocrystal and a preparation method thereof, where the semiconductor nanocrystal include a bare semiconductor nanocrystal and a water molecule...
Deep trench isolation structures and systems and methods including the
Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor...
Monolithic DMOS transistor in junction isolated process
A high voltage DMOS half-bridge output for various DC to DC converters on a monolithic, junction isolated wafer is presented. A high-side lateral DMOS...
A semiconductor device comprising a bipolar transistor and a method of making the same. A power amplifier including a bipolar transistor. The bipolar transistor...
High voltage trench transistor
A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having a gate electrode, first and second gate...
A semiconductor device includes: a silicon substrate that includes a high-concentration layer containing first conductivity type impurities; a low-concentration...
A semiconductor substrate has an element portion and a termination portion located on an outer side of the element portion. A first electrode layer is provided...
Semiconductor device including a vertical edge termination structure and
method of manufacturing
A semiconductor device includes a semiconductor body with a first surface at a first side, a second surface opposite to the first surface and an edge surface...
Semiconductor device and method of manufacturing the same
A semiconductor device is disclosed. In a surface layer of a front surface of an n-type semiconductor substrate, an anode layer is provided in an element...
Nitride crystal, nitride crystal substrate, epilayer-containing nitride
crystal substrate, semiconductor device...
A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal...
Integration techniques for MIM or MIP capacitors with flash memory and/or
high-.kappa. metal gate CMOS technology
Some embodiments of the present disclosure relate to an integrated circuit (IC) arranged on a semiconductor substrate, which includes a flash region, a...