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Patent # Description
US-9,570,386 Flexible package-to-socket interposer
A flexible interposer for the attachment of a microelectronic package to a microelectronic socket, wherein a first portion of the flexible substrate may be...
US-9,570,385 Method for fabrication of interconnection circuitry with electrically conductive features passing through a...
Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130') covered by a conductive coating (130'') which increases...
US-9,570,384 Semiconductor device
A semiconductor device can include a substrate and a trace layer positioned in proximity to the substrate and including a trace for supplying an electrical...
US-9,570,383 Semiconductor package, module substrate and semiconductor package module having the same
Semiconductor packages, module substrates and semiconductor package modules having the same are provided. The semiconductor package module includes a module...
US-9,570,382 Stackable molded microelectronic packages
A microelectronic package has a microelectronic element overlying or mounted to a first surface of a substrate and substantially rigid conductive posts...
US-9,570,381 Semiconductor packages and related manufacturing methods
Described herein are semiconductor packages having an insulating layer and the manufacturing methods thereof, wherein semiconductor packages include a die pad;...
US-9,570,380 Electronic device provided with an encapsulation structure with improved electric accessibility and method of...
An electronic device comprising: a semiconductor die integrating an electronic component; a leadframe housing the semiconductor die; a protection body, which...
US-9,570,379 Power semiconductor package with integrated heat spreader and partially etched conductive carrier
In one implementation, a power semiconductor package includes a power transistor having a first power electrode and a gate electrode on its bottom surface, and...
US-9,570,378 Semiconductor device including dummy pattern
A semiconductor device includes a substrate including a circuit region, a dummy region, and a dummy clearance section surrounding the circuit region, and a...
US-9,570,377 Semiconductor devices having through electrodes capped with self-aligned protection layers
Semiconductor devices having through electrodes capped with self-aligned protection layers. The semiconductor device comprises a semiconductor substrate...
US-9,570,376 Electrical interconnect for an integrated circuit package and method of making same
A chip package includes a first substrate having at least one circuit layer formed on a first surface thereof, a first die mounted on a second surface of the...
US-9,570,375 Semiconductor device having silicon interposer on which semiconductor chip is mounted
Disclosed herein is a device that includes a silicon interposer having wiring lines on first and second wiring layers. The wiring lines includes first, second...
US-9,570,374 Systems and methods for coupling a semiconductor device of an automation device to a heat sink
A system includes a heat sink, a semiconductor device, and a layer of thermal interface material (TIM) disposed between the heat sink and the semiconductor...
US-9,570,373 Near-chip compliant layer for reducing perimeter stress during assembly process
A heat source (single semiconductor chip or group of closely spaced semiconductor chips of similar height) is provided on a first side of a substrate, which...
US-9,570,372 Thermally enhanced semiconductor assembly with heat spreader and integrated dual build-up circuitries and...
The present invention relates to methods of making a semiconductor assembly having a semiconductor device embedded in a heat spreader and electrically connected...
US-9,570,370 Multi chip package and method for manufacturing the same
A multi chip package includes a protective layer having an upper surface that surrounds a first chip and a second chip, which are mounted over a first...
US-9,570,369 Semiconductor package with sidewall-protected RDL interposer and fabrication method thereof
A semiconductor package includes a redistributed layer (RDL) interposer having a first side, a second side opposite to the first side, and a vertical sidewall...
US-9,570,368 Method of manufacturing semiconductor package including forming a recessed region in a substrate
A method of forming a semiconductor package includes forming a passivation layer over a semiconductor substrate. The semiconductor substrate includes a first...
US-9,570,367 Ultra fine pitch PoP coreless package
A bottom package for a PoP (package-on-package) may be formed with a reinforcement layer supporting a thin or coreless substrate. The reinforcement layer may...
US-9,570,366 Passivation layer for packaged chip
A packaged IC chip includes a testing pad, wherein the testing pad is electrically connected to devices in the packaged integrated circuit chip. The packaged IC...
US-9,570,365 Display device and test pad thereof
The present disclosure provides a display device, including: a display region; and a non-display region adjacent to the display region, wherein the non-display...
US-9,570,364 Method of detecting focus shift in lithography process, method of analyzing error of transferred pattern using...
A method of detecting focus shift in a lithography process, a method of analyzing an error of a transferred pattern using the same, and a method of...
US-9,570,363 Vertically integrated memory cell
A method of forming a vertically integrated memory cell including a deep trench extending into a substrate, a trench capacitor located within the deep trench,...
US-9,570,362 Method for manufacturing semiconductor device and semiconductor device
A method for manufacturing a semiconductor device including a MOS transistor comprising forming a gate electrode on a first insulating film formed on a...
US-9,570,361 Method of fabricating a semiconductor device including high-K metal gate having reduced threshold voltage variation
A semiconductor device having a reduced variation in threshold voltage includes a semiconductor substrate with a high dielectric-constant (high-k) layer...
US-9,570,360 Dual channel material for finFET for high performance CMOS
Silicon fins are formed in a bulk silicon substrate and thereafter trench isolation regions are formed between each silicon fin. The silicon fins in nFET and...
US-9,570,359 Substrate structure, complementary metal oxide semiconductor device, and method of manufacturing complementary...
A substrate structure, a complementary metal oxide semiconductor (CMOS) device including the substrate structure, and a method of manufacturing the CMOS device...
US-9,570,358 Nano wire structure and method for fabricating the same
A method comprises applying a first patterning process to a first photoresist layer to form a first opening, a second opening, a third opening and a fourth...
US-9,570,357 Vertical field effect transistors
Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure...
US-9,570,356 Multiple gate length vertical field-effect-transistors
Various embodiments disclose a method for fabricating a semiconductor structure. In one embodiment, the method includes forming a masking layer over at least a...
US-9,570,355 Methods for contact formation for 10 nanometers and beyond with minimal mask counts
A method of making a semiconductor device includes depositing a hard mask on a dielectric layer on a substrate, the dielectric layer being disposed around...
US-9,570,354 Asymmetric high-K dielectric for reducing gate induced drain leakage
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes...
US-9,570,353 Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device is provided. The method includes forming of an interlayer insulating film on a semiconductor substrate;...
US-9,570,352 Method of dicing a wafer and semiconductor chip
A method of dicing a wafer may include forming a plurality of active regions in a wafer, each active region including at least one electronic component, the...
US-9,570,351 Reusable semiconductor substrates
In example implementations, a plurality of material layers and a plurality of etch stop layers are grown on a first substrate. Ions are implanted through at...
US-9,570,350 Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a...
US-9,570,349 Non-lithographically patterned directed self assembly alignment promotion layers
A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a...
US-9,570,348 Method of forming contact strucutre
A method of forming a contact structure is provided. A silicon-containing substrate is provided with a composite dielectric layer formed thereon. An opening...
US-9,570,347 Method of semiconductor integrated circuit fabrication
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the...
US-9,570,346 Method of manufacturing semiconductor device
A barrier metal is formed from a surface of an interlayer insulating film 2 to a trench that is formed in a semiconductor portion exposed in a contact hole....
US-9,570,345 Cobalt resistance recovery by hydrogen anneal
Resistance increase in Cobalt interconnects due to nitridation occurring during removal of surface oxide from Cobalt interconnects and deposition of...
US-9,570,344 Method to protect MOL metallization from hardmask strip process
A method can include forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the forming including...
US-9,570,343 Rinsing solution to prevent TiN pattern collapse
The present invention is a new formulation and process for treating TiN semiconductor devices having a high aspect ratio structure formed thereon. The new...
US-9,570,342 Via structure and method for its fabrication
In a preferred embodiment of the invention, the via comprises one or more stacks, each stack comprising a seed layer of a first electrically conducting material...
US-9,570,341 Semiconductor device having air gap structures and method of fabricating thereof
One method includes forming a conductive feature in a dielectric layer on a substrate for a semiconductor device. A hard mask layer and an underlying etch stop...
US-9,570,340 Method of etching a crystalline semiconductor material by ion implantation and then chemical etching based on...
The invention provides a method of etching a crystalline semiconductor material (114), the method being characterized in that it comprises: at least one ion...
US-9,570,339 Semiconductor structure and process thereof
A semiconductor process including the following step is provided. A sacrificial layer is formed in a substrate. The sacrificial layer and the substrate are...
US-9,570,338 Method for forming isolation member in trench of semiconductor substrate
A method for forming an isolation member in a trench of a substrate may include the following steps: performing a first deposition process to form a first...
US-9,570,337 Film formation apparatus and film formation method
At the time of transporting a substrate into or from a space where a film formation process is performed, the space where the film formation process is...
US-9,570,336 Substrate transfer system and substrate processing system
A substrate transfer system includes a substrate transfer robot. The substrate transfer robot is provided between a first apparatus and a second apparatus which...
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