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Semiconductor memory device and memory system
According to one embodiment, a semiconductor memory device comprises an input circuit configured to input data, a memory cell array which includes memory cells...
According to an embodiment, a memory system includes first wiring lines; second wiring lines; third wiring lines; fourth wiring lines; and first and second...
Semiconductor memory device
A semiconductor memory device includes a first memory block having a first memory cell transistor and a first select transistor, a second memory block having a...
Non-volatile memory with two phased programming
Programming non-volatile memory includes applying a series of programming pulses to the memory cells as part of a coarse/fine programming process. Between...
Semiconductor memory device and operating method thereof
The invention relates to a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a first plane and a second...
Programming dummy data into bad pages of a memory system and operating
A memory system includes a memory device including a plurality of memory blocks each including a plurality of pages, wherein the plurality of pages each include...
Nonvolatile memory device, storage device having the same, operating
An operating method of a nonvolatile memory device includes determining whether a memory block is a selected block, and when the memory block is not the...
Incrementally programmable non-volatile memory
An array of programmable non-volatile devices, such as a nominal OTP cell, is adapted such that a V.sub.t representing a particular binary logic state can be...
Coding method and decoding method in memory system
Provided are a coding/decoding method for use in a multi-level memory system. The coding method includes searching for a set of symbols that may generate a...
Semiconductor storage device and memory system
A semiconductor storage device has a memory string including a memory cell, a bit line electrically connected to one end of the memory string, and a sense...
Apparatuses and methods for providing set and reset voltages at the same
Apparatuses and methods are described, such as those involving driver circuits that are configured to provide reset and set voltages to different variable state...
Resistance change memory cell circuits and methods
The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current...
Resistive memory device and method of operating the same
A memory device includes a memory cell array having multiple memory cells arranged respectively in regions where first signal lines cross second signal lines....
Resistive memory device
A memory device includes a plurality of memory cells and a control unit. The memory cells include a first segment including a resistive memory material for...
Nonvolatile memory device with reduced coupling noise and driving method
Provided are nonvolatile memory devices and a driving method of the nonvolatile memory devices. The nonvolatile memory devices may include a plurality of memory...
Apparatuses and methods of reading memory cells
A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (V.sub.TH) region between a first state...
Read operations and circuits for memory devices having programmable
elements, including programmable resistance...
A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation...
1D-2R memory architecture
A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second...
System and method for performing memory operations on RRAM cells
A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an...
Immunity of phase change material to disturb in the amorphous phase
Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset...
Data read method for flash memory
The invention provides a data read method. In one embodiment, a flash memory comprises a plurality of pages, and predetermined information is written into each...
Method of operating incrementally programmable non-volatile memory
An array of programmable non-volatile devices, such as a nominal OTP cell, is operated such that a V.sub.t representing a particular binary logic state is...
Non-volatile storage system with defect detetction and early programming
A non-volatile storage system includes defect detection and early program termination. The system commences programming of a plurality of non-volatile memory...
Methods and apparatus to preserve data of a solid state drive during a
power loss event
Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method...
Output latch for accelerated memory access
An integrated circuit (IC) is disclosed herein for accelerating memory access with an output latch. In an example aspect, the output latch includes a data...
Dynamic capacitance balancing
Various implementations described herein are directed to a device for dynamic capacitance balancing. The device may include a sense amplifier configured to...
Data aware write scheme for SRAM
Approaches for providing write-assist for a Static Random Access Memory (SRAM) array are provided. A circuit includes a control circuit connected to a cell in a...
Circuit to improve SRAM stability
Approaches for stability of cells in a Static Random Access Memory (SRAM) array are provided. A circuit includes a precharging circuit configured to precharge...
Dual-port SRAM timing control circuit which can reduce the operational
power consumption of SRAM without...
A dual-port SRAM timing control circuit, with three NMOS transistors connected in series respectively between ground and nodes of the two bit lines to which the...
Multi-ported static random access memory
A static random access memory (SRAM) with high efficiency. The SRAM has a first bistable cell, a first bit line, a first complementary bit line, a first word...
High reliability non-volatile static random access memory devices, methods
A memory cell includes a storage element coupled to a first data node and a second data node, a first programmable nonvolatile element and a second programmable...
Semiconductor device and semiconductor system
A semiconductor device may include a data output circuit configured to sense and amplify data of an input/output line and a complementary input/output line...
Memory device with open bit line structure which minimizes loading
difference of sense amplifiers arranged...
A memory device may include: first to Nth cell blocks; first to (N-1)th bit line sense amplifiers, of which a Kth bit line sense amplifier amplifies a potential...
Output signal generation device having a phase adjustment unit and method
for adjusting a phase difference...
An output signal generation device in accordance with disclosed embodiments includes: a phase adjustment unit that generates an output signal on the basis of an...
Internal voltage generation circuit, semiconductor memory device and
semiconductor memory system
An internal voltage generation circuit includes a charging unit suitable for charging electrical charges for a time corresponding to a control signal; a charge...
Semiconductor package with PoP structure and refresh control method
A refresh control method of a semiconductor package, comprising: providing a semiconductor package including a first semiconductor chip and a second...
Alternate access to DRAM data using cycle stealing
A method for operating a DRAM is provided. The method includes initializing a dynamic random access memory ("DRAM") array from a host controller, which is...
Protocol for refresh between a memory controller and a memory device
The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device...
Memory refresh method and devices
The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently...
Semiconductor memory device for performing refresh operation
A semiconductor memory device includes: a plurality of memory areas; a target area setting unit suitable for designating a target area according to a number of...
Apparatus having dice to perorm refresh operations
Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first...
Memory device having a transistor including a semiconductor oxide
To provide a memory device which can perform verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length,...
Circuit for mixed memory storage and polymorphic logic computing
A circuit utilizing memcapacitive elements for mixed memory storage and polymorphic computing is introduced. The circuit includes a plurality of memory cells...
Magnetic state element and circuits
Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to...
Magnetic memory cells with fast read/write speed
Memory cells and methods for forming a memory cell are presented. The memory cell includes a storage unit and a selector unit. The storage unit includes a...
Magnetic memory and semiconductor-integrated-circuit
A magnetic memory includes a magnetoresistive device and a load resistance unit. The magnetoresistive device has a first resistance state and a second...
Semiconductor memory apparatus
A semiconductor memory apparatus may include a decoding control block configured to generate a first decoding control signal and a second decoding control...
Apparatuses and methods to delay memory commands and clock signals
An example delay circuit may include a delay block configured to receive a command signal and/or a bank address signal, a first clock signal, and a second clock...
Reducing transactional latency in address decoding
Techniques for reducing latency in address decoding are described. According to one approach, a method of operating an addressing circuit comprises partitioning...
Local word line driver
A memory circuit with a word line driver and control circuitry is disclosed. The word line driver receives a first voltage reference signal, a second voltage...