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Patent # Description
US-9,577,688 Frequency tuning of narrowband low noise amplifiers
A radio frequency (RF) receiver that includes a low noise amplifier (LNA), a tunable resonant circuit, and a processor for performing calibration of the RF...
US-9,577,687 Multiple interferer cancellation for communications systems
An interference cancellation system (ICS) may be used with a communication system to prevent or minimize interference from one or more sources. The ICS may...
US-9,577,686 Providing for radio frequency auto gain control (RF AGC)
A method and system for providing radio frequency auto gain control (RF AGC) for a specific frequency is provided herein. The method includes obtaining a noise...
US-9,577,685 Pre-distortion calibration
A system includes baseband circuitry and a transmitter. The electrical behavior of the transmitter may cause distortion effects in the transmit output of the...
US-9,577,684 High frequency time interleaved digital to time converter (DTC)
Described herein are technologies related to an implementation of a time interleaved digital-to-time converter (DTC) topology to generate high frequency phase...
US-9,577,683 Systems, transceivers, receivers, and methods including cancellation circuits having multiport transformers
Example apparatuses and methods for cancellation of transmitter self-interference leakage in a transceiver are described. An example transceiver includes a...
US-9,577,682 Adaptive forward error correction (FEC) system and method
In a network for reliable transfer of packets from a transmitter to a receiver using an Internet Protocol (IP), a system for packet recovery comprising a...
US-9,577,681 Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and...
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first...
US-9,577,680 Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 4/15 and...
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first...
US-9,577,679 Transmitting apparatus and signal processing method thereof
A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity...
US-9,577,678 Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 7/15 and...
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first...
US-9,577,677 Device and method for transmitting data using convolutional turbo code (CTC) encoder in mobile communication system
A method for transmitting data using a convolutional turbo code (CTC) encoder. Specifically, the method comprises: encoding input data bits, which have been...
US-9,577,675 System and method for encoding user data with low-density parity-check codes with flexible redundant parity...
A system including a first module, a second module and a third module. The first module is configured to generate a first parity check matrix. The second module...
US-9,577,674 Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and...
A bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length...
US-9,577,673 Error correction methods and apparatuses using first and second decoders
Apparatuses and methods for error correcting data are provided. A first error correction code (ECC) decoder is configured to decode a first codeword to provide...
US-9,577,672 Low density parity-check code decoder and decoding method thereof
The present disclosure illustrates a low density parity-check code decoder adapted for decoding coding data having bit nodes and check nodes. The decoder...
US-9,577,671 Parity check circuit and memory device including the same
A parity check circuit may include a first signal combination unit for generating first to N.sup.th combination signals by combining first to N.sup.th signals,...
US-9,577,670 Path encoding and decoding
This invention relates to a system, method and computer program product for encoding an input string of binary characters including: a cellular data structure...
US-9,577,669 Methods, systems, and computer readable media for optimized message decoding
Methods, systems, and computer readable media for optimized message decoding are disclosed. According to one exemplary method, the method includes receiving a...
US-9,577,668 Systems and apparatuses for performing CABAC parallel encoding and decoding
Apparatuses, systems, and computer program products that encode and/or decode information of a video stream, such as an MPEG-4 video stream, are disclosed. Some...
US-9,577,667 System and method for arithmetic encoding and decoding
An arithmetic encoder is provided for converting an event sequence comprised of a plurality of events to an information sequence comprised of at least one...
US-9,577,666 Method and system
A method includes: setting a first and a second storage regions; first creating a first compression code of a compression target data in a file using a...
US-9,577,665 Deflate compression algorithm
A compression algorithm replaces duplicative strings with a copy pair indicating a location and length of a preceding identical string that is within a window...
US-9,577,664 Efficient processing and detection of balanced codes
Circuits that are matched to balanced codes may recover transmitted information in a noise resilient and power efficient manner. Circuit components for...
US-9,577,663 Bandwidth extension of oversampled analog-to-digital converters by means of gain boosting
A digitized system operates to receive one or more analog signals from a sensor or other component and convert the analog signals to one or more digital...
US-9,577,662 Method and apparatus for excess loop delay compensation in continuous-time sigma-delta analog-to-digital converters
A CT-SDADC of the present disclosure converts the analog input signal from a representation in an analog signal domain to a representation in a digital signal...
US-9,577,661 Voltage-controlled oscillator and analog-digital converter
A voltage-controlled oscillator includes a voltage-current converter, a first ring oscillator and a second ring oscillator. The voltage-current converter...
US-9,577,660 Successive approximation ADC and control method thereof
Successive approximation ADC includes a digital-to-analog converter, a comparator, a comparison unit, a timing unit and a control logic circuit. The...
US-9,577,659 Amplifier circuit, ad converter, wireless communication device, and sensor system
An amplifier circuit has a sampling circuit to comprise a sampling capacitor which samples an input voltage and a plurality of switches, a quantizer to quantize...
US-9,577,658 Analog to digital converter and data conversion method
An analog-to-digital converter includes comparator modules and an encoder module. Each of the comparator modules is configured to compare a reference voltage...
US-9,577,657 Delta sigma patterns for calibrating a digital-to-analog converter
A digital to analog converter (DAC) maps a digital word to an analog output. The DAC bits may have amplitude and timing errors. These errors (or sometimes...
US-9,577,656 Narrowband analog noise cancellation
A method, including receiving an input analog signal containing noise at a specific noise frequency and digitizing the input analog signal to form a digitized...
US-9,577,655 Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation
Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a...
US-9,577,654 Analog-digital converter and control method
In an example embodiment, an analog-digital converter includes digital-analog converter, a comparator, and a register. The digital-analog converter is...
US-9,577,653 Quasi-linear spin torque nano-oscillators
Techniques, systems, and devices are disclosed for implementing a quasi-linear spin-torque nano-oscillator based on exertion of a spin-transfer torque on the...
US-9,577,652 Atomic resonance transition device, atomic oscillator, electronic apparatus, and moving object
An atomic resonance transition device includes a gas cell having an internal space that seals an alkali metal, a light emitter that emits excitation light...
US-9,577,651 Circuits for generating sweep frequency signal
A circuit to generate a sweep frequency signal that includes a reference frequency source to generate a reference frequency signal, a first frequency...
US-9,577,650 Phase lock loop lock indicator
A lock-on detection circuit for a phase-locked loop includes circuitry configured to receive first up and down outputs and second up and down outputs from one...
US-9,577,649 Methods and apparatus for reducing power in clock distribution networks
Integrated circuits with clock distribution circuitry are provided. The clock distribution circuitry may include a clock source, a clock distribution network, a...
US-9,577,648 Semiconductor device and method for accurate clock domain synchronization over a wide frequency range
A clock synchronization circuit has a clock sync detector. A first variable delay circuit is coupled to a first input of the clock sync detector. A controller...
US-9,577,647 Systems and methods for temperature compensated oscillators having low noise
A voltage controlled oscillator arrangement is disclosed. The arrangement includes a voltage controlled oscillator and a bypass component. The voltage...
US-9,577,646 Fractional phase locked loop (PLL) architecture
In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider...
US-9,577,645 Driver circuit for outputting photon counting including a multiplexer, inverter and power supply
A driver circuit outputs a result of classifying and counting photons based on one or more energy levels to a column line. The driver circuit includes a...
US-9,577,644 Reconfigurable logic architecture
According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies. The dies may include a memory cell die configured to...
US-9,577,643 Secure partial reconfiguration regions
Systems and methods for partially reconfiguring a programmable IC device are presented. Processing circuitry on the programmable IC device may identify a first...
US-9,577,642 Method to form a 3D semiconductor device
A method to form a 3D integrated circuit, the method including: fabricating two or more devices; connecting the devices together to form the 3D integrated...
US-9,577,641 Spin transfer torque based memory elements for programmable device arrays
Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use...
US-9,577,640 Flexible, space-efficient I/O circuitry for integrated circuits
Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads...
US-9,577,639 Source separated cell
A MOS device includes a first MOS transistor having a first MOS transistor source, a first MOS transistor drain, and a first MOS transistor gate. The MOS device...
US-9,577,638 Digital signal up-converting apparatus and related digital signal up-converting method
A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the...
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