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Patent # Description
US-9,576,981 Semiconductor device having a gate insulting film with thick portions aligned with a tapered gate electrode
By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is...
US-9,576,980 FinFET devices having gate dielectric structures with different thicknesses on same semiconductor structure
FinFET devices are formed on the same semiconductor structure wherein at least one finFET device has a gate dielectric structure that is different in thickness...
US-9,576,979 Preventing strained fin relaxation by sealing fin ends
A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective...
US-9,576,978 Cells including at least one fin field effect transistor and semiconductor integrated circuits including the same
A semiconductor integrated circuit (IC) may comprise at least one cell comprising at least one fin field-effect transistor (FET). The at least one cell may...
US-9,576,977 Semiconductor device and method of manufacturing the same
A semiconductor device includes a channel layer including a sidewall having protrusions and depressions alternating with each other in a direction in which the...
US-9,576,976 Three dimensional memory device
A 3D memory device includes a multi-layer stacks structure having a plurality of conductive strips and a first, a second, a third and a fourth ridge stack; a...
US-9,576,975 Monolithic three-dimensional NAND strings and methods of fabrication thereof
A vertically repeating stack of a unit layer stack is formed over a substrate. The unit layer stack includes a sacrificial material layer, a lower silicon oxide...
US-9,576,974 Manufacturing method of semiconductor device
A method of manufacturing a semiconductor device includes forming on a lower structure, a first stack structure in which first material layers and second...
US-9,576,973 Semiconductor device and method of manufacturing the same
Disclosed is a semiconductor device, including: stack structures including interlayer insulating patterns and conductive line patterns, which are alternately...
US-9,576,972 Semiconductor device and manufacturing method thereof
A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. Two...
US-9,576,971 Three-dimensional memory structure having a back gate electrode
A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage...
US-9,576,970 Three-dimensional semiconductor memory device
A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source...
US-9,576,969 Integrated circuit device including polycrystalline semiconductor film and method of manufacturing the same
An IC device includes a polycrystalline silicon thin film interposed between a first level semiconductor circuit and a second level semiconductor circuit which...
US-9,576,968 Semiconductor memory device with a three-dimensional stacked memory cell structure
A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a...
US-9,576,967 Method of suppressing epitaxial growth in support openings and three-dimensional memory device containing...
Memory openings and support openings are formed through an alternating stack of insulating layers and spacer material layers over a semiconductor substrate....
US-9,576,966 Cobalt-containing conductive layers for control gate electrodes in a memory structure
An alternating stack of insulating layers and sacrificial material layers can be formed over a substrate. Memory stack structures and a backside trench are...
US-9,576,965 Semiconductor device and method for fabricating the same
A semiconductor device includes a bit line disposed over a semiconductor substrate, a supporting film being perpendicular to the bit line, a first storage node...
US-9,576,964 Integrated fin and strap structure for an access transistor of a trench capacitor
At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of...
US-9,576,963 Manufacturing method of vertical channel transistor array
A manufacturing method of a vertical channel transistor array is provided. The method includes following steps. A plurality of embedded word lines are formed at...
US-9,576,962 Memory device having electrically floating body transistor
A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least...
US-9,576,961 Semiconductor devices with sidewall spacers of equal thickness
Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a...
US-9,576,960 Structure for finFET CMOS
According to an embodiment, the invention provides an nFET/pFET pair of finFETs formed on a gate stack. At least one fin extends into a source drain region of...
US-9,576,959 Semiconductor device having first and second gate electrodes and method of manufacturing the same
Provided is a semiconductor device having first and second gate electrodes. The semiconductor device includes a substrate, an active region extending in a first...
US-9,576,958 Forming a semiconductor structure for reduced negative bias temperature instability
An approach to forming a semiconductor structure with improved negative bias temperature instability includes forming an interfacial layer on a semiconductor...
US-9,576,957 Self-aligned source/drain contacts
A semiconductor substrate includes lower source/drain (S/D) regions. A replacement metal gate (RMG) structure is arranged upon the semiconductor substrate...
US-9,576,956 Method and structure of forming controllable unmerged epitaxial material
A method of forming a semiconductor device that includes forming a plurality of semiconductor pillars. A dielectric spacer is formed between at least one set of...
US-9,576,955 Semiconductor device having strained channel layer and method of manufacturing the same
Semiconductor devices are provided. The semiconductor devices include active fins including a buffer layer disposed on a substrate and a channel layer disposed...
US-9,576,954 POC process flow for conformal recess fill
A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a...
US-9,576,953 Layout design system, semiconductor device fabricated by using the system and method for fabricating the...
A layout design system for designing a semiconductor device includes a processor, a storage module storing an intermediate design, and a correction module used...
US-9,576,952 Integrated circuits with varying gate structures and fabrication methods
Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the...
US-9,576,951 Devices formed from a non-polar plane of a crystalline material and method of making the same
Materials, methods, structures and device including the same can provide a semiconductor device such as an LED using an active region corresponding to a...
US-9,576,950 Contacts to transition metal dichalcogenide and manufacturing methods thereof
A device includes a transition metal dichalcogenide layer having a first edge with a zigzag atomic configuration. A metallic material has a portion overlapping...
US-9,576,949 Diode formed of PMOSFET and schottky diodes
A P-type Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) includes a gate, a first source/drain region connected to the gate, and a second...
US-9,576,948 Semiconductor device
A semiconductor device includes a first and second transistor. Each of the first and the second transistors includes a well of a first conductivity type, a...
US-9,576,947 Semiconductor integrated circuit device
In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the...
US-9,576,946 Semiconductor device and method of manufacturing same
A method of manufacturing a semiconductor device, comprising: providing a substrate; forming a first trough structure, which comprises at least a first...
US-9,576,945 Methods and apparatus for increased holding voltage in silicon controlled rectifiers for ESD protection
Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well...
US-9,576,944 Semiconductor devices with transistor cells and thermoresistive element
A semiconductor device includes a first load terminal electrically coupled to a source zone of a transistor cell. A gate terminal is electrically coupled to a...
US-9,576,943 Apparatuses and methods of communicating differential serial signals including charge injection
Apparatuses and methods are disclosed, including an apparatus that includes a differential driver with charge injection pre-emphasis. One such apparatus...
US-9,576,942 Integrated circuit assembly that includes stacked dice
An integrated circuit assembly that includes a substrate; a member formed on the substrate; a first die mounted to the substrate within an opening in the member...
US-9,576,941 Light-emitting device and method of manufacturing the same
A light-emitting device includes a plurality of light-emitting elements face-down mounted on a substrate, a plurality of structures each including a transparent...
US-9,576,940 Light emitting device and LCD backlight using the same
The present invention provides a light emitting device which comprises blue and red light emitting diode (LED) chips and at least one phosphor for emitting...
US-9,576,939 Light emitting device and lighting system having the same
The present invention provides a light emitting device comprising a first light emitting portion that emits white light at a color temperature of 6000K or more...
US-9,576,938 3DIC packages with heat dissipation structures
A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion...
US-9,576,937 Back-to-back stacked integrated circuit assembly
An integrated circuit assembly includes a first substrate and a second substrate, with active layers formed on the first surfaces of each substrate, and with...
US-9,576,936 Semiconductor system having semiconductor apparatus and method of determining delay amount using the...
A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in response...
US-9,576,935 Method for fabricating a semiconductor package and semiconductor package
A method for fabricating semiconductor packages includes providing a first substrate having an aperture, providing a first semiconductor chip, connecting the...
US-9,576,934 Semiconductor device
A semiconductor device according to the present invention includes: a through via formed to penetrate a semiconductor substrate; first and second buffer...
US-9,576,933 Fan-out wafer level packaging and manufacturing method thereof
A fan-out wafer-level-package (FOWLP) is provided. The FOWLP includes a redistribution layer (RDL) comprising a dielectric layer and a first metal layer; a...
US-9,576,932 Universal surface-mount semiconductor package
In the fabrication of semiconductor packages, a leadframe is formed by masking and etching a metal sheet from both sides, and a plastic block is formed over a...
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