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Patent # Description
US-9,576,931 Method for fabricating wafer level package
A method for fabricating a wafer level package is disclosed. A carrier is provided. A redistributed layer (RDL) layer is formed on the carrier. Semiconductor...
US-9,576,930 Thermally conductive structure for heat dissipation in semiconductor packages
A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the...
US-9,576,929 Multi-strike process for bonding
A method includes performing a first strike process to strike a metal bump of a first package component against a metal pad of a second package component. A...
US-9,576,928 Bond head assemblies, thermocompression bonding systems and methods of assembling and operating the same
A bond head assembly for bonding a semiconductor element to a substrate is provided. The bond head assembly includes a base structure, a heater, and a clamping...
US-9,576,927 Bonding tool cooling apparatus and method for cooling bonding tool
A bonding tool cooling apparatus (10) provided in the vicinity of a bonding stage, including a frame (12); a cooling member (16) including a ground plate (14)...
US-9,576,926 Pad structure design in fan-out package
A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors...
US-9,576,925 Semiconductor device having a cylindrical shaped conductive portion
A semiconductor device includes a first conductive portion, a second conductive portion, a first layer, and a second layer. The first conductive portion...
US-9,576,924 Semiconductor device and a method of manufacturing the same
A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating...
US-9,576,923 Semiconductor chip with patterned underbump metallization and polymer film
Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is...
US-9,576,922 Silver alloying post-chip join
A method of forming a stacked surface arrangement for semiconductor devices includes joining a first surface to a second surface with a solder bump, the solder...
US-9,576,921 Semiconductor device and manufacturing method for the same
To improve an integration degree of a semiconductor device. The semiconductor device includes a plurality of wiring layers formed on the semiconductor...
US-9,576,920 Moisture barrier for semiconductor structures with stress relief
A semiconductor structure is disclosed. The semiconductor structure includes an electrically conductive layer disposed over a substrate. A moisture barrier...
US-9,576,919 Semiconductor device and method comprising redistribution layers
A method of making a semiconductor package can include forming a plurality of redistribution layer (RDL) traces disposed over active surfaces of a plurality of...
US-9,576,918 Conductive paths through dielectric with a high aspect ratio for semiconductor devices
Conductive paths through a dielectric are described that have a high aspect ratio for semiconductor devices. In one example, a plurality of conductive...
US-9,576,917 Embedded die in panel method and structure
Methods for an embedded die panel are disclosed and may include fabricating a first layered structure by: forming first redistribution layers on a first...
US-9,576,916 High frequency circuit comprising graphene and method of operating the same
A high frequency circuit includes a first electronic device, a second electronic device, and a graphene interconnection unit, where at least one of a trench and...
US-9,576,915 IC-package interconnect for millimeter wave systems
Consistent with an example embodiment, a System on Chip (SoC) device operates in millimeter wave frequencies. The SoC device comprises, a silicon device having...
US-9,576,914 Inducing device variation for security applications
A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and regions, with implant regions and covered regions, in the...
US-9,576,913 Semiconductor device and manufacturing method of semiconductor device
A semiconductor device that improves noise performance includes a circuit substrate, an enclosing case, and a metal part. A control circuit is mounted on the...
US-9,576,912 Wafer level chip scale package (WLCSP) having edge protection
A wafer level chip scale package (WLCSP) includes a semiconductor substrate, a back end of line (BEOL) layer on the semiconductor substrate and having a...
US-9,576,911 Radio frequency module including segmented conductive ground plane
A radio frequency (RF) module comprises an electrical reference, or ground, plane to which one or more RF devices disposed on the module are electrically...
US-9,576,910 Semiconductor packaging structure and manufacturing method thereof
A semiconductor structure includes a plurality of devices; a molding surrounding the plurality of devices and including a first surface adjacent to an active...
US-9,576,909 Bumpless die-package interface for bumpless build-up layer (BBUL)
Embodiments of the present disclosure are directed towards bumpless interfaces to an embedded silicon die, in integrated circuit (IC) package assemblies. In one...
US-9,576,908 Interconnection structure, fabricating method thereof, and semiconductor device using the same
A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface...
US-9,576,907 Wiring structure and method of manufacturing the same
A wiring structure is made up by electrically connecting a via part made up by forming CNTs in a via hole and a wiring part made up of multilayer graphene on an...
US-9,576,906 Methods related to a sputtered titanium tungsten layer formed over a copper interconnect stack structure
Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a stack disposed over a compound semiconductor,...
US-9,576,905 Semiconductor device and manufacturing method thereof
A semiconductor device includes a first wiring comprising a first conductive material on a semiconductor layer, a second wiring comprising the first conductive...
US-9,576,904 Semiconductor devices comprising interconnect structures and methods of fabrication
Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of...
US-9,576,903 Structure with conductive plug and method of forming the same
Provided is a structure with a conductive plug including a substrate, a first dielectric layer, an etch stop layer, a second dielectric layer, a conductive plug...
US-9,576,902 Semiconductor device including landing pad
A semiconductor device includes conductive lines spaced from a substrate, and an insulating spacer structure between the conductive lines and defining a contact...
US-9,576,901 Contact area structure and method for manufacturing the same
A method for manufacturing a semiconductor device includes forming a contact area opening in a dielectric structure, depositing a contact area metal in the...
US-9,576,900 Switched power stage with integrated passive components
A scalable switching regulator architecture has an integrated inductor. In some embodiments an area and current drive capability of switches of the switching...
US-9,576,899 Electrical fuse with high off resistance
Electrical fuses and methods for forming an electrical fuse. A semiconductor substrate is implanted to define a modified region in the semiconductor substrate....
US-9,576,898 Resistance structure, integrated circuit, and method of fabricating resistance structure
A resistance structure including: a conductive layer provided at a surface layer portion of a semiconductor substrate; a first resistance element having long...
US-9,576,897 Semiconductor interconnect device
A method for forming an interconnect device is provided by the present disclosure. The method includes providing a dielectric layer on a substrate, forming...
US-9,576,896 Semiconductor arrangement and formation thereof
A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes an interconnect which includes an interconnect metal...
US-9,576,895 Semiconductor device with damascene bit line and method for fabricating the same
A semiconductor device includes a substrate having a plurality of contact surfaces, an interlayer dielectric layer formed over the substrate and having a first...
US-9,576,894 Integrated circuits including organic interlayer dielectric layers and methods for fabricating the same
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes...
US-9,576,893 Semiconductor structure and semiconductor fabricating process for the same
A semiconductor structure and a fabricating process for the same are provided. The semiconductor fabricating process includes providing a first dielectric...
US-9,576,892 Semiconductor devices and methods of forming same
Embodiments of the present disclosure include a semiconductor device and methods of forming the same. An embodiment is a method for of forming a semiconductor...
US-9,576,891 Isolation device
An isolation device for isolating a first signal of a first circuit from a second circuit disclosed. The isolation device may have a substrate and a plurality...
US-9,576,890 Semiconductor device and method of manufacturing the same
Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a...
US-9,576,889 Three-dimensional electronic packages utilizing unpatterned adhesive layer
An electronic package may be fabricated by forming a first layer of insulating material on a first substrate such that the first layer covers a contact pad;...
US-9,576,888 Package on-package joint structure with molding open bumps
A device comprises a bottom package comprising a plurality of metal bumps formed on a first side of the bottom package and a plurality of first bumps formed on...
US-9,576,887 Semiconductor package including conductive carrier coupled power switches
In one implementation, a semiconductor package including conductive carrier coupled power switches includes a first vertical FET in a first active die having a...
US-9,576,886 Flat no-lead packages with electroplated edges
A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet...
US-9,576,885 Semiconductor device
A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal...
US-9,576,884 Low profile leaded semiconductor package
In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the...
US-9,576,883 Semiconductor devices and methods of making the same
In one embodiment, methods for making semiconductor devices are disclosed.
US-9,576,882 Through polymer via (TPV) and method to manufacture such a via
Vias for three dimensional (3D) stacking, packaging and heterogeneous integration of semi-conductor layers and wafers and a process for the manufacture of a...
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