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Patent # Description
US-9,576,830 Method and apparatus for adjusting wafer warpage
A method for adjusting the warpage of a wafer, includes providing a wafer having a center portion and edge portions and providing a holding table having a...
US-9,576,829 Process liquid supply apparatus operating method, process liquid supply apparatus and non-transitory storage medium
According to an embodiment of the present disclosure, a process liquid supply apparatus operating method is provided. The method includes filling a filter unit...
US-9,576,828 Heat reservoir chamber, and method for thermal treatment
The present disclosure provides a thermal treatment chamber. The thermal treatment chamber includes a wafer holder to hold a to-be-processed wafer; a heat...
US-9,576,827 Apparatus and method for wafer level bonding
A system for and a method of bonding a first wafer to a second wafer are provided. A second wafer chuck has a second surface, a profile of the second surface...
US-9,576,826 Systems and methods for controlling wafer-breaker devices
Systems and methods for controlling wafer-breaker devices. In some embodiments, a controller for a semiconductor wafer singulation apparatus can be configured...
US-9,576,825 Device for alignment of two substrates
Device and method for alignment of a first contact surface of a first substrate with a second contact surface of a second substrate which can be held on a...
US-9,576,824 Etching chamber with subchamber
In an apparatus for etching a semiconductor wafer or sample (101), the semiconductor wafer or sample is placed on a sample holder (104) disposed in a first...
US-9,576,823 Methods of forming a microshield on standard QFN package
Shielded electronic packages may have metallic lead frames to connect an electromagnetic shield to ground. In one embodiment, a metallic lead frame of the...
US-9,576,822 Encapsulated dies with enhanced thermal performance
The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip...
US-9,576,821 Package structures including a capacitor and methods of forming the same
A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side...
US-9,576,820 Semiconductor structure and method of manufacturing the same
A method of manufacturing a chip fan-out structure, said method includes forming a dry film with a predetermined pattern. Providing a chip wherein the...
US-9,576,819 Techniques for increased dopant activation in compound semiconductors
A method of doping a compound semiconductor substrate includes: setting a first substrate temperature for the compound semiconductor substrate in a first...
US-9,576,818 Polishing slurry for cobalt removal
Provided herein are polishing compositions for removal of Co, for example, selectively over Cu, and methods of their use. A polishing composition comprising an...
US-9,576,817 Pattern decomposition for directed self assembly patterns templated by sidewall image transfer
After forming spacers over a hard mask layer using a sidewall image transfer process, a neutral material layer is formed on the portions of the hard mask layer...
US-9,576,816 Method for roughness improvement and selectivity enhancement during arc layer etch using hydrogen
A method of patterning a silicon containing ARC (anti-reflective coating) layer underlying a patterned layer is described that includes establishing a flow of a...
US-9,576,815 Gas-phase silicon nitride selective etch
A method of etching silicon nitride on patterned heterogeneous structures is described and includes a gas phase etch using anhydrous vapor-phase HF. The HF may...
US-9,576,814 Method of spacer patterning to form a target integrated circuit pattern
A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the...
US-9,576,813 Method of fabricating semiconductor device
Provided is a method of fabricating a semiconductor device. In the method, a double patterning technology is used to form various patterns with different widths.
US-9,576,812 Partial etch memorization via flash addition
Provided is a method of creating structure profiles on a substrate using faceting and passivation layers. A first plasma etch process performed generating a...
US-9,576,811 Integrating atomic scale processes: ALD (atomic layer deposition) and ALE (atomic layer etch)
Methods are provided for integrating atomic layer etch and atomic layer deposition by performing both processes in the same chamber or reactor. Methods involve...
US-9,576,810 Process for etching metal using a combination of plasma and solid state sources
An apparatus configured to remove metal etch byproducts from the surface of substrates and from the interior of a substrate processing chamber. A plasma is used...
US-9,576,809 Etch suppression with germanium
Methods of selectively etching silicon relative to silicon germanium are described. The methods include a remote plasma etch using plasma effluents formed from...
US-9,576,808 Substrate processing apparatus and substrate processing method
In a substrate processing apparatus, with an internal space of a chamber brought into a pressurized atmosphere, an etching process is performed by continuously...
US-9,576,807 Wafer polishing apparatus and method
Disclosed is a wafer processing apparatus. The wafer processing apparatus includes a first surface plate on which a plurality of carriers is arranged, a first...
US-9,576,806 FinFET device with vertical silicide on recessed source/drain epitaxy regions
A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel...
US-9,576,805 Fortification of charge-storing material in high-K dielectric environments and resulting apparatuses
Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel...
US-9,576,804 System and method for mitigating oxide growth in a gate dielectric
Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in...
US-9,576,803 Method for tuning metal gate work function before contact formation in fin-shaped field effect transistor...
The present invention provides a method for metal gate work function tuning before contact formation in a fin-shaped field effect transistor (FinFET), where in...
US-9,576,802 Semiconductor device and method for manufacturing the same
A method for manufacturing a semiconductor device is disclosed. The method comprises: forming a T-shape dummy gate structure on the substrate; removing the...
US-9,576,801 High dielectric constant/metal gate (HK/MG) compatible floating gate (FG)/ferroelectric dipole non-volatile memory
Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased...
US-9,576,800 Method of producing epitaxial silicon wafer, epitaxial silicon wafer, and method of producing solid-state image...
Provided is an epitaxial silicon wafer free of epitaxial defects caused by dislocation clusters and COPs with reduced metal contamination achieved by higher...
US-9,576,799 Doping of a substrate via a dopant containing polymer film
Disclosed herein is a method for doping a substrate, comprising disposing a coating of a composition comprising a copolymer, a dopant precursor and a solvent on...
US-9,576,798 Method for fabricating semiconductor layers including transistor channels having different strain states, and...
Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor...
US-9,576,797 Method of fabricating polysilicon layer, thin film transistor, organic light emitting diode display device...
A method of fabricating a polysilicon layer includes forming a buffer layer on a substrate, forming a metal catalyst layer on the buffer layer, diffusing a...
US-9,576,796 Semiconductor devices and methods of manufacture thereof
A method of manufacturing a semiconductor device may include: forming an opening in an insulating layer to expose a portion of a major surface of a substrate,...
US-9,576,795 Semiconductor device
An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for...
US-9,576,794 Cyclical deposition of germanium
In some aspects, methods for forming a germanium thin film using a cyclical deposition process are provided. In some embodiments, the germanium thin film is...
US-9,576,793 Semiconductor wafer and method for manufacturing the same
An embodiment of a method for manufacturing a semiconductor wafer includes providing a monocrystalline silicon wafer, epitaxially growing a first layer of a...
US-9,576,792 Deposition of SiN
Methods and precursors for forming silicon nitride films are provided. In some embodiments, silicon nitride can be deposited by atomic layer deposition (ALD),...
US-9,576,791 Semiconductor devices including semiconductor structures and methods of fabricating the same
Semiconductor devices and methods for fabricating semiconductor devices are provided. In one example, a semiconductor device includes a semiconductor structure....
US-9,576,790 Deposition of boron and carbon containing materials
Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B, C films with desirable properties, such as...
US-9,576,789 Apparatus, method, and composition for far edge wafer cleaning
A wafer cleaning apparatus includes a polishing unit used in chemical mechanical polishing (CMP) of a wafer and a cleaning dispensing unit arranged to direct...
US-9,576,788 Cleaning high aspect ratio vias
A method of removing an amorphous silicon/silicon oxide film stack from vias is described. The method may involve a remote plasma comprising fluorine and a...
US-9,576,787 Substrate treatment method
A substrate treatment method includes a substrate holding unit which horizontally holds a substrate; a rotating unit which rotates the substrate held by the...
US-9,576,786 Intelligent radio-controlled plasma light
The user of plasma light technology and remote lighting control techniques may enable a single master controller to control a large number of lighting fixtures....
US-9,576,785 Electrodeless single CW laser driven xenon lamp
An ignition facilitated electrodeless sealed high intensity illumination device is disclosed. The device is configured to receive a laser beam from a continuous...
US-9,576,784 Electrical gas-discharge lamp with discharge-coupled active antenna
The present invention relates to an electrical gas-discharge lamp comprising an inner bulb (1) arranged within an outer bulb (2), said inner bulb (1) being...
US-9,576,783 Time-of-flight mass spectrometers with cassini reflector
The invention relates to embodiments of high-resolution time-of-flight (TOF) mass spectrometers with special reflectors. The invention provides reflectors with...
US-9,576,782 Orthogonal acceleration system for time-of-flight mass spectrometer
An orthogonal pulse accelerator for a Time-of-Flight mass analyzer includes an electrically-conductive first plate extending in a first plane, and a second...
US-9,576,781 Intelligent dynamic range enhancement
A method of mass spectrometry is disclosed comprising transmitting ions and obtaining first mass spectral data and automatically determining during an...
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