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Patent # Description
US-9,576,678 Shift register group and method for driving the same
A shift register group includes a plurality of series-coupled shift registers each being configured to provide an output signal. The third control signal of a...
US-9,576,677 Scan driving circuit
A scan driving circuit is disclosed, and the scan driving circuit has a pull-up control module, a pull-up module, a pull-down module, a pull-down maintaining...
US-9,576,676 Semiconductor device and method of writing data
A semiconductor device includes: an electric fuse circuit including first electric fuses used as data bits and second electric fuses used as polarity bits; and...
US-9,576,675 Non-volatile semiconductor memory having multiple external power supplies
A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to...
US-9,576,674 Memory cell sensing
This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line,...
US-9,576,673 Sensing multiple reference levels in non-volatile storage elements
Disclosed herein are techniques for sensing multiple reference levels in non-volatile storage elements without changing the voltage on the selected word line....
US-9,576,672 Non-volatile memory device and related method of operation
A nonvolatile memory device comprises a cell array connected to a plurality of bit lines in an all bit line structure, a page buffer circuit connected to the...
US-9,576,671 Calibrating optimal read levels
After a predetermined period of time in a life cycle of a flash memory device, a plurality of reliability values corresponding to a plurality of reads of one or...
US-9,576,670 Method and system for managing a writing cycle of a data in a EEPROM memory cell
An operation for writing at least one datum in at least one memory cell of the electrically erasable and programmable read-only memory type comprises at least...
US-9,576,669 Nonvolatile memory devices and methods of programming and reading nonvolatile memory devices
In a method of programming a nonvolatile memory device, a program operation is performed on a selected memory cell coupled to a selected word line in response...
US-9,576,668 Semiconductor device and operating method thereof
The semiconductor device includes a memory block including programmed pages and non-programmed pages, a peripheral circuit configured to perform a read...
US-9,576,667 Apparatuses and methods for non-volatile memory programming schemes
Apparatuses and methods for a non-volatile memory scheme are described herein. An example apparatus may include a memory block including a plurality of...
US-9,576,666 Non-volatile memory device, operating method thereof, memory system including the non-volatile memory device,...
An operating method of a non-volatile memory device having a string including a plurality of memory cells and a plurality of auxiliary cells, the plurality of...
US-9,576,665 Semiconductor memory device and memory system
A semiconductor memory device includes: a first string unit including first and second memory cell transistors; a second string unit including third and fourth...
US-9,576,664 Three dimensional semiconductor memory device
A semiconductor memory device may include a string including at least one drain select transistor, a plurality of first memory cells, a first connection...
US-9,576,663 Multi-port memory
Multi-port memory circuitry includes single-port memory circuitry, and arbitration logic circuitry that accepts multiple memory queries for the single-port...
US-9,576,662 Phase change memory in a dual inline memory module
Subject matter disclosed herein relates to management of a memory device.
US-9,576,661 Systems and methods for SRAM with backup non-volatile memory that includes MTJ resistive elements
A memory device has an SRAM that stores a logic state. A first MTJ has two terminals. A second one of the terminals is coupled to a storing node. A first...
US-9,576,660 Low forming voltage non-volatile storage device
A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across...
US-9,576,659 Apparatuses and methods including memory access in cross point memory
Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch...
US-9,576,658 Systems, and devices, and methods for programming a resistive memory cell
Embodiments disclosed herein may relate to programming a memory cell with a programming pulse that comprises a quenching period having different portions. The...
US-9,576,657 Memory cells including vertically oriented adjustable resistance structures
A memory cell is provided that includes a vertically-oriented adjustable resistance structure including a control terminal coupled to a word line, and a...
US-9,576,656 Device and method for setting resistive random access memory cell
A device and method for setting a resistive random access memory cell are provided. An exemplary method includes: providing a set current to a bit line of the...
US-9,576,655 Apparatus and method for programming a multi-level phase change memory (PCM) cell based on an actual resistance...
An apparatus for programming at least one multi-level Phase Change Memory (PCM) cell having a first terminal and a second terminal. A programmable control...
US-9,576,654 Apparatuses, sense circuits, and methods for compensating for a wordline voltage increase
Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a...
US-9,576,653 Fast sense amplifier with bit-line pre-charging
A bit-line of a resistive memory cell includes a reference branch including a reference resistor having a predetermined value and a cell branch including an...
US-9,576,652 Resistive random access memory apparatus with forward and reverse reading modes
The invention provides a resistive memory apparatus including at least one first resistive memory cell, a first bit line selecting switch, a first source line...
US-9,576,651 RRAM and method of read operation for RRAM
According to one embodiment, a method of RRAM operations is provided. The method includes the following operations: providing a first voltage difference across...
US-9,576,650 Read measurement of a plurality of resistive memory cells for alleviating resistance and current drift
A method for read measurement of a plurality N of resistive memory cells having a plurality M of programmable levels is suggested. The method includes a step of...
US-9,576,649 Charge loss compensation through augmentation of accumulated charge in a memory cell
Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a block of solid-state non-volatile...
US-9,576,648 Method and apparatus for decoding memory
A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such...
US-9,576,647 Parallel programming of nonvolatile memory cells
Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In...
US-9,576,646 SRAM cell with dynamic split ground and split wordline
An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor...
US-9,576,645 Three dimensional dual-port bit cell and method of using same
A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port...
US-9,576,644 Integrated circuit chip having two types of memory cells
An integrated circuit chip includes a first type memory cell and a second type memory cell. The first type memory cell includes a first reference line landing...
US-9,576,643 Array power supply-based screening of static random access memory cells for bias temperature instability
A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory...
US-9,576,642 Memory device with dynamically operated reference circuits
This invention concerns a semiconductor memory device comprising: at least one sense amplifier circuit for reading data sensed from selected memory cells in a...
US-9,576,641 Semiconductor device verifying signal supplied from outside
Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an...
US-9,576,640 Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system
A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and...
US-9,576,639 Method for controlling a semiconductor device having CAL latency function
One semiconductor device includes a command receiver receiving the command signal to generate a first internal command signal, and a latency control circuit...
US-9,576,638 Information processing apparatus, control method for the same, program for the same, and storage medium
An information processing apparatus according to an aspect of the present invention acquires temperature information for each of a plurality of memories in a...
US-9,576,637 Fine granularity refresh
A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor is adapted to access at least one rank...
US-9,576,636 Magnetic memory having ROM-like storage and method therefore
A magnetoresistive memory device that stores data in the reference portion of spin-torque memory cells provides for more robust data storage. In normal...
US-9,576,635 Thermally-assisted magnetic writing device
A thermally-assisted magnetic writing device includes at least one magnetic element including: a reference layer having a stable vortex magnetization...
US-9,576,634 Magnetic tunnel junction based chip identification
The present invention provides integrated circuit chips having chip identification aspects. The chips include magnetic tunnel junction (MTJ) structures, and...
US-9,576,633 Method and system for programming magnetic junctions utilizing high frequency magnetic oscillations
A magnetic memory and methods for providing and programming the magnetic memory are described. The memory includes storage cells, magnetic oscillator(s) and bit...
US-9,576,632 Magnetic storage device
A magnetic storage device of one embodiment includes a first and second magnetoresistive effect elements. The first magnetoresistive element includes a first...
US-9,576,631 Spin hall effect magnetic apparatus, method and applications
An ST-MRAM structure, a method for fabricating the ST-MRAM structure and a method for operating an ST-MRAM device that results from the ST-MRAM structure each...
US-9,576,630 Memory devices and methods having multiple address accesses in same cycle
A memory device can include a plurality of banks, each bank including memory locations accessible by different access circuits; at least a first address port...
US-9,576,629 Memory device and memory system including the same, and operation method of memory device
A memory device includes a memory cell array having a plurality of memory cells, a storage unit suitable for storing a fail address corresponding to a fail...
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