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Patent # Description
US-9,583,634 Semiconductor device and method for manufacturing the same
To provide a semiconductor device which has transistor characteristics with little variation and includes an oxide semiconductor. The semiconductor device...
US-9,583,633 Oxide for semiconductor layer of thin film transistor, thin film transistor and display device
In an oxide for a semiconductor layer of a thin film transistor according to the present invention, wherein metal elements constituting the oxide are In, Zn,...
US-9,583,632 Oxide semiconductor film, method for forming oxide semiconductor film, and semiconductor device
A crystalline oxide semiconductor film and a semiconductor device including the oxide semiconductor film are provided. One embodiment of the present invention...
US-9,583,631 Transistors with uniform density of poly silicon
A transistor with uniform density of poly silicon includes a gate terminal, a drain terminal, and a source terminal. The gate terminal is constructed by a...
US-9,583,630 Method for producing semiconductor device and semiconductor device
A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate, and forming a...
US-9,583,629 Semiconductor device
According to one embodiment, a first transistor includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first gate...
US-9,583,628 Semiconductor device with a low-K spacer and method of forming the same
A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer. Low-k...
US-9,583,627 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a fin-shaped structure...
US-9,583,626 Silicon germanium alloy fins with reduced defects
A silicon germanium alloy is formed on sidewall surfaces of a silicon fin. An oxidation process or a thermal anneal is employed to convert a portion of the...
US-9,583,625 Fin structures and multi-Vt scheme based on tapered fin and method to form
A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt...
US-9,583,624 Asymmetric finFET memory access transistor
A field effect transistor device comprises a semiconductor substrate, a doped source layer arranged on the semiconductor substrate, an insulator layer arranged...
US-9,583,623 Semiconductor device including fin structures disposed over buffer structures and manufacturing method thereof
A semiconductor FET device includes a buffer structure and a fin structure. The buffer structure has a fin shape, is disposed over a substrate and extends along...
US-9,583,622 Semiconductor structure and method for manufacturing the same
The present invention discloses a semiconductor structure and a method for manufacturing the same, which comprises providing a substrate, and forming a stress...
US-9,583,621 Semiconductor device and method of manufacturing the same
Provided are a semiconductor device and a method of manufacturing the same. An example device may include: a fin formed on a substrate; a gate stack formed on...
US-9,583,620 Shaped cavity for SiGe filling material
The present invention is directed to semiconductor processes and devices. More specifically, embodiments of the present invention provide a semiconductor device...
US-9,583,619 Semiconductor devices with shaped cavities for embedding germanium material and manufacturing processes thereof
The present invention is directed to semiconductor processes and devices. More specifically, embodiments of the present invention provide a shaped cavity that...
US-9,583,618 Metal oxide semiconductor field effect transistor having asymmetric lightly doped drain regions
A metal-oxide-semiconductor field effect transistor (MOSFET) includes a substrate and a gate structure over a top surface of the substrate. The MOSFET further...
US-9,583,617 Semiconductor device and method of forming the same
Provided is a semiconductor device including a substrate, an insulating layer, a conductive layer and at least one spacer. The substrate has at least two...
US-9,583,616 Semiconductor structure including backgate regions and method for the formation thereof
A semiconductor structure includes a semiconductor substrate, a plurality of transistors and an electrically insulating layer provided between the substrate and...
US-9,583,615 Vertical transistor and local interconnect structure
A first patterned stack and a second patterned stack are formed over a substrate, each of which includes a bottom semiconductor layer, a bottom dielectric...
US-9,583,614 Insulated gate field effect transistor having passivated schottky barriers to the channel
A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is...
US-9,583,613 Metal oxide semiconductor devices and fabrication methods
A semiconductor device includes a first well that is disposed in a semiconductor substrate. The semiconductor device further includes a second well that is...
US-9,583,612 Drift region implant self-aligned to field relief oxide with sidewall dielectric
An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region....
US-9,583,611 Trench MOSFET having reduced gate charge
A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the...
US-9,583,610 Transistor and method of manufacturing the same
A method of forming a manufacture includes forming a trench in a doped layer; and forming a gate dielectric layer along sidewalls of an upper portion of the...
US-9,583,609 MOS transistor structure and method of forming the structure with vertically and horizontally-elongated metal...
Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions...
US-9,583,608 Nitride semiconductor device and method for manufacturing nitride semiconductor device
A nitride semiconductor device of the present invention has a source-electrode-side insulator protection film layer disposed between a source electrode and a...
US-9,583,607 Semiconductor device with multiple-functional barrier layer
A semiconductor device includes a semiconductor structure forming a carrier channel, a barrier layer arranged in proximity with the semiconductor structure, and...
US-9,583,606 Semiconductor device
An improvement is achieved in the reliability of a semiconductor device having an IGBT. In an active cell region, in a portion of a semiconductor substrate...
US-9,583,605 Method of forming a trench in a semiconductor device
A method to make a semiconductor device, a first SiO.sub.2 layer and a first Si.sub.3N.sub.4 layer are sequentially formed on the semiconductor substrate. The...
US-9,583,604 Semiconductor device with improved short circuit capability
A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device,...
US-9,583,603 ESD protection with integrated LDMOS triggering junction
An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a base region in the semiconductor substrate and having a first...
US-9,583,602 Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and...
Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling...
US-9,583,601 Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device including a transistor with stable electrical characteristics or high reliability is provided. A gate...
US-9,583,600 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and...
US-9,583,599 Forming a fin using double trench epitaxy
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a fin using double trench epitaxy....
US-9,583,598 FETs and methods of forming FETs
An embodiment is a structure. The structure comprises a fin on a substrate, isolation regions on the substrate, a dielectric region, and a gate structure. The...
US-9,583,597 Asymmetric FinFET semiconductor devices and methods for fabricating the same
Asymmetric FinFET devices and methods for fabricating such devices are provided. In one embodiment, a method includes providing a semiconductor substrate...
US-9,583,596 Drain extended CMOS with counter-doped drain extension
An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS...
US-9,583,595 Methods of forming low noise semiconductor devices
Disclosed herein are Lateral Diffused Metal Oxide Semiconductor (LDMOS) device and trench isolation related devices, methods, and techniques. In one...
US-9,583,594 Method of fabricating semiconductor device
A semiconductor device and a method of fabricating the same, the semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer...
US-9,583,593 FinFET and method of manufacturing the same
A FinFET and a method of manufacturing the same are disclosed. The method includes forming a semiconductor fin. The method further includes forming a first...
US-9,583,592 Methods of manufacturing semiconductor devices
In a method of manufacturing a semiconductor device, a dummy gate structure is formed on a substrate. A first spacer layer is formed on the substrate to cover...
US-9,583,591 Si recess method in HKMG replacement gate technology
The present disclosure relates to a method of embedding an ESF3 memory in a HKMG integrated circuit that utilizes a replacement gate technology. The ESF3 memory...
US-9,583,590 Integrated circuit devices including FinFETs and methods of forming the same
Methods of forming a finFET are provided. The methods may include forming a fin-shaped channel region including indium (In) on a substrate, forming a deep...
US-9,583,589 Self-aligned double gate recess for semiconductor field effect transistors
A method for fabricating a double-recess gate structure for an FET device that includes providing a semiconductor wafer having a plurality of semiconductor...
US-9,583,588 Method of making high electron mobility transistor structure
A method includes epitaxially growing a gallium nitride (GaN) layer over a silicon substrate. The method further includes epitaxially growing a donor-supply...
US-9,583,587 Method for manufacturing injection-enhanced insulated-gate bipolar transistor
A method for manufacturing an injection-enhanced insulated-gate bipolar transistor, comprising the following steps: an n-type substrate (12) is provided; a...
US-9,583,586 Transient voltage suppressor (TVS) with reduced breakdown voltage
A low capacitance transient voltage suppressor with snapback control and a reduced voltage punch-through breakdown mode includes an n+ type substrate, a first...
US-9,583,585 Gate structure integration scheme for fin field effect transistors
In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure...
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