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Patent # Description
US-9,583,534 Semiconductor device including magneto-resistive device
A semiconductor device comprises a magneto-resistive device capable of performing multiple functions with low power. The semiconductor device comprises a cell...
US-9,583,533 LED device with embedded nanowire LEDs
A nanowire device and a method of forming a nanowire device that is poised for pick up and transfer to a receiving substrate are described. In an embodiment,...
US-9,583,532 Solid-state image sensing device and method of manufacturing the same
By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film...
US-9,583,531 Process for transferring circuit layer
A process for transferring a buried circuit layer comprises taking a donor substrate comprising an internal etch stop zone and covered on its front side with a...
US-9,583,530 X-ray detector
To provide an X-ray detector facilitating the installing and replacement work of a module while reducing the possibility of breakage. An X-ray detector 50...
US-9,583,529 Next generation imaging methods and systems
Novel imaging arrangements are detailed. One comprises an optical array sensor with plural photo-electron generating regions dispersed at two or more layers in...
US-9,583,528 Solid-state imaging device
A MOS solid-state imaging device is provided in which withstand voltage and 1/f noise of a MOS transistor are improved. In the MOS solid-state imaging device...
US-9,583,527 Contact resistance reduction
An image sensor includes a plurality of photodiodes disposed in a semiconductor material and a floating diffusion disposed in the semiconductor material...
US-9,583,526 Solid-state image pickup element and solid-state image pickup element mounting structure
A solid-state image pickup element is provided with a semiconductor substrate having a photosensitive region, a plurality of first electrode pads arrayed on a...
US-9,583,525 Die stacked image sensors and related methods
An image sensor. Implementations may include: a first die including a plurality of pixels; a second die including a plurality of transistors, capacitors, or...
US-9,583,524 Optical imaging system that incorporates an uni-axial optical homogenizer
An optical imaging system (e.g., hyperspectral imaging system) is described herein which includes imaging optics, an uni-axial homogenizer (including a...
US-9,583,523 Photoelectric conversion device and imaging system
A photoelectric conversion device includes a photoelectric conversion unit disposed above a substrate and a reading circuit. The photoelectric conversion unit...
US-9,583,522 Image sensor and electronic device including the same
Disclosed are an image sensor including a light collection member having a multi-layer step shape and an electronic device including the same. This technology...
US-9,583,521 Solid-state image pickup device
A solid-state image pickup device has a first substrate and a second substrate in which circuit elements constituting pixels are arranged. The pixel includes: a...
US-9,583,520 Optimizing geometric fill factor in prism-coupled waveguide-fed solar collector
A prism coupled waveguide-fed solar collector array optimized for geometric fill factor. An integrated linear array of prisms is arranged with their input faces...
US-9,583,519 Manufacturing method of a thin film transistor and pixel unit thereof
The present invention provides a method of manufacturing a thin film transistor pixel unit, comprising: forming a metal oxide layer, a gate insulating layer, a...
US-9,583,518 Display device and method of manufacturing the same
A display device and a method of manufacturing the same are disclosed, in which a sensing electrode for sensing a touch of a user is built in a display panel,...
US-9,583,517 Polycrystalline oxide thin-film transistor array substrate and method of manufacturing same
This invention provides a polycrystalline oxide thin-film transistor (TFT) array substrate and a method of manufacturing the same. As the polycrystalline oxide...
US-9,583,516 Display device
A display device having a high aperture ratio and including a capacitor that can increase capacitance is provided. A pair of electrodes of the capacitor is...
US-9,583,515 Semiconductor device including substrate which is used in display devices
A semiconductor device (100T, 100B) includes: a substrate (30); a first metal layer (10) supported on the substrate (30), the first metal layer (10) including a...
US-9,583,514 Thin film transistor array substrate
The present invention relates to a thin film transistor array substrate and a method of manufacturing the same. The thin film transistor array substrate may...
US-9,583,513 Display device
By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case...
US-9,583,512 Array substrate and manufacturing method thereof, and display panel
The disclosure relates to an array substrate and a manufacturing method thereof, and a display panel. The array substrate includes a plurality of data lines and...
US-9,583,511 Array substrate having integrated gate driver and method of fabricating the same
An array substrate includes: a substrate; a gate connecting line on the substrate in a gate circuit area; a gate insulating layer on the gate connecting line;...
US-9,583,510 Semiconductor device, display device, and method for manufacturing semiconductor device
A semiconductor device (100A) includes a first metal layer (12) including a gate electrode (12g); a gate insulating layer (14) formed on the first metal layer;...
US-9,583,509 Semiconductor device wherein an oxide semiconductor layer has a degree of crystallization of 80% or more
An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to...
US-9,583,508 Array substrate, preparation method for array substrate, and display device
The present invention discloses an array substrate, a preparation method for the array substrate, and a display device, wherein the array substrate comprises a...
US-9,583,507 Adjacent strained <100> NFET fins and <110> PFET fins
The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of forming strained <100> n-channel...
US-9,583,506 Semiconductor memory device and method of manufacturing the same
According to an embodiment, a semiconductor memory device comprises a stacked body, a semiconductor layer, a charge accumulation layer, and a first layer. The...
US-9,583,505 Non-volatile memory device
According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first...
US-9,583,504 Non-volatile storage device and method of manufacturing the same
According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality...
US-9,583,503 Three-dimensional semiconductor device and method of manufacturing the same
A three-dimensional semiconductor device is provided, comprising: a plurality of ground selection line (GSL) sections separately formed on a substrate, the GSL...
US-9,583,502 Method of manufacturing a semiconductor device
After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a...
US-9,583,501 Simultaneous formation of a top oxide layer in a silicon-oxide-nitride-oxide-silicon (SONOS) transistor and a...
A semiconductor chip includes a base of a memory transistor in a first region of a substrate, and a base of a metal oxide semiconductor (MOS) transistor in a...
US-9,583,500 Multilevel memory stack structure and methods of manufacturing the same
A first stack of alternating layers including first electrically conductive layers and first electrically insulating layers is formed with first stepped...
US-9,583,499 Devices with embedded non-volatile memory and metal gates and methods for fabricating the same
Devices and methods for fabricating devices with floating gates and replacement metal gates are provided. In an embodiment, a method for fabricating a device...
US-9,583,498 Structure and method for BEOL nanoscale damascene sidewall-defined non-volatile memory element
An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to...
US-9,583,497 Metal trench capacitor and improved isolation and methods of manufacture
A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one...
US-9,583,496 Memory device with manufacturable cylindrical storage node
A high capacitance embedded capacitor and associated fabrication processes are disclosed for fabricating a capacitor stack in a multi-layer stack to include a...
US-9,583,495 Method for fabricating memory device
Provided is a method for fabricating a memory device including forming a stack layer on a substrate, and embedding a plurality of gate pillar structures and a...
US-9,583,494 Apparatus and method for integrated circuit bit line sharing
A memory array includes a first memory column having a first bit line, a first word line and a second bit line. The memory array also includes a second memory...
US-9,583,493 Integrated circuit and semiconductor device
An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different...
US-9,583,492 Structure and method for advanced bulk fin isolation
A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor...
US-9,583,491 CMOS nanowire structure
Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The...
US-9,583,490 Inverters and manufacturing methods thereof
Inverters and methods of manufacture thereof are disclosed. In some embodiments, an inverter includes a substrate and a first tunnel FET (TFET) disposed over...
US-9,583,489 Solid state diffusion doping for bulk finFET devices
A method of forming a semiconductor device comprises forming a first fin on a substrate, depositing an insulator layer on the substrate adjacent to the first...
US-9,583,488 Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow
An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and...
US-9,583,487 Semiconductor device having metallic source and drain regions
Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above...
US-9,583,486 Stable work function for narrow-pitch devices
A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the...
US-9,583,485 Fin field effect transistor (FinFET) device structure with uneven gate structure and method for forming the same
A FinFET device structure is provided. The FinFET device structure includes an isolation structure formed over a substrate and a fin structure formed over the...
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