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Integrated device package comprising conductive sheet configured as an
inductor in an encapsulation layer
An integrated device package includes a package substrate, a die coupled to the package substrate, an encapsulation layer encapsulating the die, and at least...
Interconnects through dielecric vias
A dielectric layer includes a reflow via. The reflow via is formed by reflow of the dielectric layer. An interconnect is in contact through the reflow via.
2.5D electronic package
A 2.5D electronic package is provided in which at least one integrated circuit is mounted on an interposer that is mounted on a package substrate. To reduce...
The inventive concepts provide package-on-package (PoP) devices. In the PoP devices, an interposer substrate and a thermal boundary material layer may be...
Interconnect structure and method of forming same
A method comprises depositing a first dielectric layer over a substrate, forming a first metal line and a second metal line in the first dielectric layer,...
Embedding thin chips in polymer
Systems and methods are provided for the embedding of thin chips. A well region is generated in a substrate that includes a conductive material disposed on a...
Semiconductor substrate, semiconductor package structure and method of
making the same
The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a...
Multi-layer substrates suitable for interconnection between circuit
An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs 112). The interposer includes a substrate...
Solder fatigue arrest for wafer level package
A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some...
Integrated circuit structure and method for reducing polymer layer
An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the...
Semiconductor device and method of manufacturing the same
A semiconductor device includes a stacked structure including conductive layers and insulating layers stacked alternately with each other, first semiconductor...
A lead frame, as one product unit in a multi-row lead frame sharing a partition frame among other lead frames, has a non-mirrorsymmetric pad region and at least...
Recessed lead leadframe packages
Leadframes for semiconductor packages. Implementations may include a plurality of leads extending inwardly into an opening surrounded by the plurality of leads...
Semiconductor device and method of manufactures
A semiconductor device and method of manufacture is provided. A reflowable material is placed in electrical connection with a through via, wherein the through...
Semiconductor constructions having through-substrate interconnects
Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor...
Chip embedded package method and structure
A chip embedded package method is provided by an embodiment of the present invention. The method comprises: etching metallic sinks on the thicker metal layer of...
Via structure for signal equalization
An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has a first surface and a second surface opposite the first...
Mounting structure of semiconductor device and method of manufacturing the
A semiconductor-device mounting structure includes a first semiconductor device and a plate-shaped second semiconductor device connected to the first...
Packages with thermal interface material on the sidewalls of stacked dies
A package includes a die stack that includes at least two stacked dies, and a Thermal Interface Material (TIM). The TIM includes a top portion over and...
Silicon-on-plastic semiconductor device and method of making the same
A semiconductor device that does not produce nonlinearities attributed to a high resistivity silicon handle interfaced with a dielectric region of a buried...
A semiconductor device includes a first chip coupled to an electrical insulator, and a sintered heat conducting layer disposed between the electrical insulator...
A semiconductor device includes a substrate having an edge, a semiconductor layer provided on a substrate, an electrode pad provided on the semiconductor layer,...
Fine pitch BVA using reconstituted wafer with area array accessible for
A method for simultaneously making a plurality of microelectronic packages by forming an electrically conductive redistribution structure along with a plurality...
Volumetric integrated circuit and volumetric integrated circuit
A volumetric integrated circuit manufacturing method is provided. The method includes assembling a slab element of elongate chips, exposing a wiring layer...
Resin sealed module
A resin-sealed module is provided which reduces the warpage of a substrate and the detachment between a sealing resin and the substrate which occur during...
Reducing directional stress in an orthotropic encapsulation member of an
Methods and apparatuses for reducing directional stress in an orthotropic encapsulation member of an electronic package may include attaching a stiffening frame...
A first conductor layer is provided on a first surface of an insulating plate, and has a first volume. A second conductor layer is provided on a second surface...
System and method for dual-region singulation
A method for semiconductor fabrication includes forming a first array of semiconductor circuitry and a second array of semiconductor circuitry separated by a...
Endpointing detection for chemical mechanical polishing based on
Methods and apparatus for spectrum-based endpointing. An endpointing method includes selecting a reference spectrum. The reference spectrum is a spectrum of...
Implementing resistance defect performance mitigation using test signature
directed self heating and increased...
A method and system are provided for implementing resistive defect performance mitigation for integrated circuits. A test is generated for identifying resistive...
Method of manufacturing a semiconductor device using semiconductor
A method includes loading a substrate into a sensing chamber; while the substrate is in the sensing chamber, performing a spectral analysis of the substrate;...
Nano deposition and ablation for the repair and fabrication of integrated
An apparatus for and methods of repairing and manufacturing integrated circuits using the apparatus. The apparatus, comprising: a vacuum chamber containing: a...
Gate stack with tunable work function
A method for fabricating a gate stack of a semiconductor device comprising forming a first dielectric layer over a channel region of the device, forming a...
Semiconductor device and manufacturing method thereof
A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer...
Integrated circuit having FinFETS with different fin profiles
An integrated circuit is provided. The integrated circuit includes a substrate, a first FinFET device supported by the substrate, the first FinFET device having...
Source/drain terminal contact and method of forming same
One aspect of the disclosure relates to a contact within a dielectric layer to a source/drain terminal of a field-effect-transistor (FET). The contact may...
Making a defect free fin based device in lateral epitaxy overgrowth region
Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of...
Method for manufacturing a semiconductor switching device with different
local cell geometry
A method for manufacturing a semiconductor device includes providing a semiconductor substrate having an outer rim, an active area, and an edge termination...
Manufacturing method of semiconductor structure
The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, having a first fin structure and a...
Epitaxial growth of doped film for source and drain regions
Embodiments of mechanisms for epitaxially growing one or more doped silicon-containing materials to form source and drain regions of finFET devices are provided...
Carbon layer and method of manufacture
A system and method for manufacturing a carbon layer is provided. An embodiment comprises depositing a first metal layer on a substrate, the substrate...
Wafer processing method
There is provided a wafer processing method including a modified layer forming step. In the wafer processing method, the power of a pulse laser beam set in the...
Organic thin film passivation of metal interconnections
Electronic assemblies and their manufacture are described. One embodiment relates to a method including depositing an organic thin film layer on metal bumps on...
Selective area deposition of metal films by atomic layer deposition (ALD)
and chemical vapor deposition (CVD)
Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of...
Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an...
Multilevel mask circuit fabrication and multilayer circuit
Circuit fabrication uses a multilevel mask to pattern a first conductor layer of a multilayer circuit. The first conductor patterning is to provide electrical...
Interlevel conductor pre-fill utilizing selective barrier deposition
A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench...
Method for producing ultra-thin tungsten layers with improved step
A tungsten nucleation film is formed on a surface of a semiconductor substrate by alternatively providing to that surface, reducing gases and ...
Via corner engineering in trench-first dual damascene process
An integrated circuit structure includes a first dielectric layer, an etch stop layer over the first dielectric layer, and a second dielectric layer over the...
Air gap forming techniques based on anodic alumina for interconnect
An aluminum (Al) layer is formed over a semiconductor substrate. A selective portion of the Al layer is removed to form openings. The Al layer is anodized to...