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Packaging business intelligence documents with embedded data
A system and method for managing business intelligence data is described. In some example embodiments, the system extracts data and metadata from a business...
Method and apparatus for performing a FFT computation
A method, apparatus, and computer program product for performing an FFT computation. The method includes: providing first and second input data elements in...
Instruction set to enable efficient implementation of fixed point fast
fourier transform (FFT) algorithms
A computer implemented method and system for providing a Fast Fourier Transform (FFT) capability to a fixed point processor architecture is disclosed. In a...
Conjugate gradient solvers for linear systems
A conjugate gradient solver apparatus is provided for generating data defining a solution vector x for a linear system represented by Ax=b where A is a...
Method and apparatus for performing calculations in character input mode
of electronic device
A method and apparatus for performing calculations in a character input mode of an electronic device. Character input is received in the character input mode,...
Antenna apparatus and software for emulating same
According to an embodiment, there is provided a plurality of spiral antenna elements that are generated using algorithms taught herein that can be implemented...
System and methods for determining attributes for arithmetic operations
with fixed-point numbers
The present application is directed to determining attributes for results of arithmetic operations with fixed-point numbers. An indication is received of...
Capacity estimating apparatus for secondary battery
A capacity estimating apparatus for a secondary battery includes a current-detecting section configured to detect a value of current flowing in the secondary...
Normalizing data for fast superscalar processing
A data normalization system is described herein that represents multiple data types that are common within database systems in a normalized form that can be...
Vector register file
An aspect includes accessing a vector register in a vector register file. The vector register file includes a plurality of vector registers and each vector...
Flexible processors and flexible memory
An apparatus includes but is not limited to a non-volatile memory array and a processor integrated with the apparatus. The processor is operable to operate in...
Systems, apparatuses, and methods for performing a double blocked sum of
Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response...
Heterogeneous input/output (I/O) using remote direct memory access (RDMA)
and active message
Methods and apparatus to provide heterogeneous I/O (Input/Output) using RDMA (Remote Direct Memory Access) and/or Active Message are described. In an...
Computer system and method for sharing computer memory
A computer system has a plurality of computer servers, each including at least one central processing unit (CPU). A memory appliance is spaced remotely from the...
Apparatus for increasing social interaction over an electronic network
In an example, an electronic device is configured to: associate a set of member actions of an electronic social networking system with an account corresponding...
Methods for using temporal proximity of social connection creations to
predict properties of a social connection
Aspects of the subject technology relate to a social-networking system, including one or more computers communicatively coupled via a network. In certain...
List digest operation dispersed storage network frame
A method begins generating a plurality of list digest request frames. Each list digest request frames includes a payload section and a protocol header. The...
Generation of a random sub-space of the space of assignments for a set of
generative attributes for...
System, method and computer readable medium are described. The method may include obtaining user defined distribution traits characterizing a random sub-space...
Camera control interface extension bus
System, methods and apparatus are described that include a serial bus, including a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control...
A finite state machine is provided that both serializes virtual GPIO signals and deserializes virtual GPIO signals. The finite state machine frames the...
System and method for abstracting SATA and/or SAS storage media devices
via a full duplex queued command...
A simplified host accesses SATA and SAS storage media devices by abstracting the SATA and SAS protocols with one full duplex protocol that supports full command...
Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended...
I/O card architecture based on a common controller
The embodiments provide a backplane for a storage device that is readily extensible to accommodate a range storage media. In some embodiments, the controller is...
Sensor network using pulse width modulated signals
A device includes a bus interface to couple to a shared bus of a sensor network. The device also includes a sensor interface to couple to a sensor of the sensor...
In accordance with an embodiment, a receiver includes a first state machine configured to be coupled to a bus. The first state machine is configured to...
Rack, server and assembly comprising such a rack and at least one server
A rack with a mounting bay to accommodate servers, wherein 1) the mounting bay defines two opposing internal areas disposed parallel to an insertion direction...
An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or...
Transmission apparatus and control unit
A transmission apparatus includes a processor, a bridge connected to the processor, a device that is connected to the bridge but is not connected to a reset...
System, apparatus, and method for MIL-STD-1553B communication enforcement
A switch configured to enforce MIL-STD-1553B communication protocol is provided. The protocol is a request-response protocol allowing a bus controller to send a...
Device for distributing data about a vehicle
A device for distributing data about a vehicle, has a first sensor data reception interface for receiving first sensor data from a first sensor, a second sensor...
USB drive security systems and methods
Systems and methods are presented for detecting, by a universal serial bus (USB) drive operatively coupled with a computing device, power from the computing...
Selective partition based redirection for multi-partitioned USB devices
Universal serial bus (USB) devices may be redirected to a server to create USB virtual devices. Each of the USB devices to be redirected may have one or more...
Serial control channel processor for executing time-based instructions
The present disclosure describes a serial control channel processor. In some aspects, a time-based instruction corresponding to a command is executed and a...
Intercomponent data communication between different processors
A request to send a message from a first component, located on a first processor, to a second component, located on a second processor, is received. It is...
Clockless serial slave device
Various methods and devices involving a slave device are discussed. The slave device, which may be without a clock input, receives a clock message and generates...
Credit based low-latency arbitration with data transfer
An apparatus includes multiple data sources and arbitration circuitry. The data sources are configured to send to a common destination data items and respective...
Nonvolatile memory system and operating method thereof
A nonvolatile memory system includes a nonvolatile memory; a buffer memory having first and second buffers; and a memory controller configured to manage the...
Method and apparatus for identifying cause of interrupt
A method of identifying a cause of an interrupt related to an interrupt indication received from an interrupt indicating circuit in a processor, includes the...
Apparatus and method for copying rules between devices
Devices, systems, and methods are described for allowing rules that are applied to one device to be applied to another device based on a user's interaction with...
Memory system and method for efficient padding of memory pages
In one embodiment, a memory system is provided comprising a memory die and a controller. The memory die comprises a non-volatile memory, a data latch, and an...
Enhanced security for accessing virtual memory
A disclosed method includes obtaining a physical address corresponding to a virtual address responsive to detecting a virtual address associated with a memory...
Disk array flushing method and disk array flushing apparatus
A disk array flushing method and a disk array flushing apparatus. The method includes acquiring a sequence, which is according to physical addresses of logical...
Instruction and logic for support of code modification in translation
A processor includes a core with logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory...
Storage address space to NVM address, span, and length mapping/converting
Storage address space to NVM address, span, and length mapping/converting is performed by a controller for a solid-state storage system that includes a mapping...
Asymmetric set combined cache
Embodiments are generally directed to an asymmetric set combined cache including a direct-mapped cache portion and a multi-way cache portion. A processor may...
Multi-core data array power gating cache restoral programming mechanism
An apparatus including a device programmer, a stores, and a plurality of cores. The device programmer programs a semiconductor fuse array with compressed...
Multi-core programming apparatus and method for restoring data arrays
following a power gating event
An apparatus includes a device programmer and a plurality of cores. The programmer programs a semiconductor fuse array with compressed configuration data. Each...
Implementing selective cache injection
A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a...
Hardware managed compressed cache
A computing element, system, and method for implementing control structures for a compressed cache in hardware. Embodiments provide a first engine configured to...
Set selection of a set-associative storage container
A computer-implemented method includes generating a vector that is a random number. Two or more residue functions are applied to the vector to produce a state...