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Patent # Description
US-9,590,129 Optical sensor module
An optical sensor module is disclosed. The optical sensor module can include a housing comprising an air cavity. An optical emitter die can be disposed in the...
US-9,590,128 Particle detector and method of detecting particles
A particle detector having a support member. A front electrode layer is disposed over the support member. A semiconductor junction having at least an n-type...
US-9,590,127 Dual conversion gain image sensor cell
An image sensor cell formed inside and on top of a substrate of a first conductivity type, including: a read region of the second conductivity type; and,...
US-9,590,126 Solar cell assembly II
The present invention relates to a solar cell assembly that includes a solar cell attached to a bonding pad and a cooling substrate, wherein the bonding pad is...
US-9,590,124 Photoelectric conversion device, device and array device
A photoelectric conversion device including a transparent substrate, a first electrode, at least a photoelectric conversion layer and a second electrode is...
US-9,590,123 Solar modules, supporting layer stacks and methods of fabricating thereof
A solar cell supporting layer stack for mechanically supporting a solar cell is described. The solar cell includes: a rigid foam layer; one or more skin layers...
US-9,590,122 Fish eye lens analyzer
An imaging device is disclosed. The imaging device has a housing, a detector positioned within the housing and has a field of view encompassing one or more...
US-9,590,121 Optoelectronic device, and image sensor and electronic device including the same
An optoelectronic device includes a first electrode and a second electrode facing each other, a photoelectric conversion layer between the first electrode and...
US-9,590,120 MOS capacitors structures for variable capacitor arrays and methods of forming the same
A capacitor structure is described. A capacitor structure including a substrate; a source/drain region formed in the substrate to form an active area having an...
US-9,590,119 Decoupling capacitor and method of making same
A device comprises a semiconductor substrate having first and second implant regions and an electrode above and between the first and second implant regions of...
US-9,590,118 Wafer with SOI structure having a buried insulating multilayer structure and semiconductor device structure
The present disclosure provides, in a first aspect, a semiconductor device structure, including an SOI substrate comprising a semiconductor base substrate, a...
US-9,590,117 Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge...
US-9,590,115 Semiconductor device
A semiconductor device includes a first conductor, a second conductor, a first insulator, a second insulator, a third insulator, a semiconductor, and an...
US-9,590,114 Semiconductor device and method of manufacturing the same
A semiconductor device is provided, comprising a substrate with a first insulating film formed thereon, and a transistor formed on the first insulating film....
US-9,590,113 Multilayer passivation or etch stop TFT
The present invention generally relates to TFTs and methods for fabricating TFTs. For either back channel etch TFTs or for etch stop TFTs, multiple layers for...
US-9,590,112 Semiconductor device
An object is to provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability. In a transistor...
US-9,590,111 Semiconductor device and display device including the semiconductor device
A highly reliable semiconductor device including an oxide semiconductor is provided. The concentration of impurities contained in an oxide semiconductor of a...
US-9,590,110 Ultraviolet light sensor circuit
A sensor circuit with high sensitivity to ultraviolet light. Ultraviolet light is detected using a transistor containing an oxide semiconductor. When the...
US-9,590,109 Semiconductor device and method for manufacturing the same
A semiconductor device that operates at high speed. A semiconductor device with favorable switching characteristics. A highly integrated semiconductor device. A...
US-9,590,108 Gate-all-around fin device
A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality...
US-9,590,107 III-V gate-all-around field effect transistor using aspect ratio trapping
Embodiments of the invention provide methods for forming III-V gate-all-around field effect transistors on silicon substrates that utilize Aspect-Ratio Trapping...
US-9,590,106 Semiconductor device including epitaxially formed buried channel region
A semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The at least one semiconductor fin includes a channel region...
US-9,590,105 Semiconductor device with metal alloy over fin, conductive layer over channel region of fin, and semiconductive...
A semiconductor device and methods of formation are provided. The semiconductor device includes a first metal alloy over a first active region of a fin and a...
US-9,590,104 Gate device over strained fin structure
A method for forming a semiconductor device includes forming a fin structure on a substrate, forming a shallow trench isolation region adjacent the fin...
US-9,590,103 Semiconductor devices having multiple gate structures and methods of manufacturing such devices
A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate...
US-9,590,102 Semiconductor device and manufacturing method thereof
A method for manufacturing a semiconductor device includes forming a fin structure including a well layer, an oxide layer disposed over the well layer and a...
US-9,590,101 FinFET with multiple dislocation planes and method for forming the same
A method comprises forming a first fin and a second fin over a substrate, wherein the first fin and the second fin are separated by a trench, applying a first...
US-9,590,100 Semiconductor devices containing an epitaxial perovskite/doped strontium titanate structure
Semiconductor devices are provided such as, ferroelectric transistors and floating gate transistors, that include an epitaxial perovskite/doped strontium...
US-9,590,099 Semiconductor devices having gate structures and methods of manufacturing the same
Semiconductor devices are provided including an active layer, a gate structure, a spacer, and a source/drain layer. The active layer is on the substrate and...
US-9,590,098 Method for producing semiconductor device and semiconductor device
A method for producing a semiconductor device includes a first step of forming a first insulating film around the fin-shaped semiconductor layer; a second step...
US-9,590,097 Semiconductor devices and related fabrication methods
Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body region of...
US-9,590,096 Vertical FET having reduced on-resistance
In one implementation, a vertical field-effect transistor (FET) includes a substrate having a drift region situated over a drain, a body region situated over...
US-9,590,095 Semiconductor device with field electrode structures in a cell area and termination structures in an edge area
A semiconductor device includes field electrode structures regularly arranged in lines in a cell area and forming a first portion of a regular pattern....
US-9,590,094 Semiconductor device with power transistor cells and lateral transistors and method of manufacturing
By thermal oxidation a field oxide layer is formed that lines first and second trenches that extend from a main surface into a semiconductor layer. After the...
US-9,590,093 Semiconductor device
In general, according to one embodiment, a semiconductor device includes, a first semiconductor region, a plurality of second semiconductor regions, a plurality...
US-9,590,092 Super junction field effect transistor with internal floating ring
A Super Junction Field Effect Transistor (FET) device includes a charge compensation region disposed on a substrate of semiconductor material. The charge...
US-9,590,091 Minority carrier conversion structure
According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in...
US-9,590,090 Method of forming channel of gate structure
A method of forming a channel of a gate structure is provided. A first epitaxial channel layer is formed within a first trench of the gate structure. A dry...
US-9,590,089 Variable gate width for gate all-around transistors
Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to...
US-9,590,088 Current aperture vertical electron transistors with ammonia molecular beam epitaxy grown p-type gallium nitride...
A current aperture vertical electron transistor (CAVET) with ammonia (NH.sub.3) based molecular beam epitaxy (MBE) grown p-type Gallium Nitride (p-GaN) as a...
US-9,590,087 Compound gated semiconductor device having semiconductor field plate
A transistor includes a source, a drain spaced apart from the source, and a heterostructure body having a two-dimensional charge carrier gas channel for...
US-9,590,086 Buffer stack for group IIIA-N devices
A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group...
US-9,590,085 Method and structure for III-V FinFET
A method for fabricating a semiconductor device comprises forming a fin in a layer of III-V compound semiconductor material on a silicon-on-insulator substrate;...
US-9,590,084 Graded heterojunction nanowire device
A device includes a source region, a drain region, and a semiconductor channel connecting the source region to the drain region. The semiconductor channel...
US-9,590,083 ITC-IGBT and manufacturing method therefor
An ITC-IGBT and a manufacturing method therefor. The method comprises: providing a heavily doped substrate, forming a Ge.sub.xSi.sub.1-x/Si multi-quantum well...
US-9,590,082 Integration of heterojunction bipolar transistors with different base profiles
Device structures and fabrication methods for a heterojunction bipolar transistor. A first base layer is formed on a first device region of a substrate. A first...
US-9,590,081 Method of making a graphene base transistor with reduced collector area
A method of making a graphene base transistor with reduced collector area comprising forming a graphene material layer, forming a collector material, depositing...
US-9,590,079 Use disposable gate cap to form transistors, and split gate charge trapping memory cells
A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate...
US-9,590,078 Semiconductor device fabrication method and semiconductor device
A semiconductor device fabrication method includes forming a tunnel insulating film on a substrate containing silicon, forming a floating gate on the tunnel...
US-9,590,077 Local SOI fins with multiple heights
A semiconductor structure is provided that contains silicon fins having different heights, while maintaining a reasonable fin height to width ratio for process...
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