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Patent # Description
US-9,589,972 Ultraviolet-erasable nonvolatile semiconductor device
An ultraviolet-erasable nonvolatile semiconductor device has a protective film comprised of a silicon nitride film on which is laminated a silicon oxynitride...
US-9,589,971 Anti-fuse one-time programmable memory cell and anti-fuse one-time programmable memory array
An anti-fuse memory cell is provided. The anti-fuse memory cell includes a programmable transistor and a selection transistor. The programmable transistor...
US-9,589,970 Antifuse one-time programmable memory
An antifuse one-time programmable (OTP) memory cell includes a semiconductor substrate, an isolation region, and a fin structure protruding from a top surface...
US-9,589,969 Semiconductor device and manufacturing method of the same
Semiconductor devices and manufacturing methods of the same are disclosed. The semiconductor device includes a die, a conductive structure, a bonding pad and a...
US-9,589,968 Method for producing one-time-programmable memory cells and corresponding integrated circuit
An integrated circuit includes a silicon on insulator substrate having a semiconductor film located above a buried insulating layer. At least one memory cell of...
US-9,589,967 Fast programming antifuse and method of manufacture
The embodiments described herein provide an antifuse that includes a substrate material and an isolation trench formed in the substrate material, where the...
US-9,589,966 Static random access memory
A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells comprises: a gate...
US-9,589,965 Controlling epitaxial growth over eDRAM deep trench and eDRAM so formed
Methods of forming polysilicon-filled deep trenches for an eDRAM are provided. The method may include forming a plurality of polysilicon-filled deep trenches in...
US-9,589,964 Methods of fabricating semiconductor devices
A method of fabricating a semiconductor device with conductive patterns comprises sequentially forming an etch-target layer and a middle mold layer on a...
US-9,589,963 Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor
Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory...
US-9,589,962 Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias
A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions...
US-9,589,961 Semiconductor device including write access transistor having channel region including oxide semiconductor
Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory...
US-9,589,960 Semiconductor device having buried gate structure, method for manufacturing the same, memory cell having the...
A method for forming a semiconductor structure includes forming a trench in a semiconductor substrate; forming a first dielectric layer over a bottom surface...
US-9,589,959 Compensated well ESD diodes with reduced capacitance
An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance,...
US-9,589,958 Pitch scalable active area patterning structure and process for multi-channel finFET technologies
A method is disclosed which cuts hard mask fins thinner than the target fin critical dimension and then enlarges the dimension of the fin hard mask critical...
US-9,589,957 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film...
US-9,589,956 Semiconductor device with different fin pitches
A method for forming a semiconductor device includes forming a first fin and a second fin on a substrate, the first fin arranged in parallel with the second...
US-9,589,955 System on chip
Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a...
US-9,589,954 Semiconductor device having recess filled with insulating material provided between source/drain impurity...
Electric-field concentration in the vicinity of a recess is suppressed. A gate insulating film is provided on a substrate that has a drain region and a first...
US-9,589,953 Reverse bipolar junction transistor integrated circuit
A Reverse Bipolar Junction Transistor (RBJT) integrated circuit comprises a bipolar transistor and a parallel-connected distributed diode, where the base region...
US-9,589,952 Reverse conducting IGBT
A reverse conducting IGBT is provided with a trench gate member that is provided in an IGBT region and has a lattice-pattern layout, and a trench member that is...
US-9,589,951 High-electron-mobility transistor with protective diode
Performance of a semiconductor device is improved. The semiconductor device includes a substrate composed of silicon, a semiconductor layer composed of p-type...
US-9,589,950 Display apparatus
A display apparatus includes a timing controller configured to output a gate control signal through gate control lines, a gate driver configured to output gate...
US-9,589,949 Electro-static discharge protection in integrated circuit based amplifiers
An apparatus having a plurality of power pads of an integrated circuit, a plurality of transistors, and one or more diodes is disclosed. Each transistors may...
US-9,589,948 Semiconductor device
A semiconductor device has first and second NMOS transistors and an internal circuit, all formed in the same semiconductor substrate. The first NMOS transistor...
US-9,589,947 Semiconductor packages and methods of manufacturing the same
Provided are semiconductor devices and methods of manufacturing the same. The semiconductor package includes a substrate, a first semiconductor chip mounted on...
US-9,589,946 Chip with a bump connected to a plurality of wirings
According to one embodiment, a semiconductor device includes a first semiconductor chip; a first wiring and a second wiring which are provided above a first...
US-9,589,945 Semiconductor package having stacked semiconductor chips
A semiconductor package includes a package base substrate, at least one first semiconductor chip disposed on the package base substrate, and at least one...
US-9,589,944 Method and structure for receiving a micro device
A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a...
US-9,589,943 Method for separating regions of a semiconductor layer
The invention relates to a method for separating regions of a semiconductor layer and for introducing an outcoupling structure into an upper side of the...
US-9,589,942 Package structure and manufacturing method thereof
A package structure includes a first substrate, a patterned solder mask, first thermal-conductive posts, a chip and a second substrate. The first substrate...
US-9,589,941 Multi-chip package system and methods of forming the same
In an embodiment, a semiconductor structure includes a multi-chip package system (MCPS). The MCPS includes one or more dies, a molding compound extending along...
US-9,589,940 Light emitting device
A light emitting device includes a substrate, a first light emitting element, a second light emitting element, a first conductive pattern, and a second...
US-9,589,939 Optoelectronic semiconductor chip
An optoelectronic semiconductor chip includes an interconnection layer with a first electrically conductive contact layer, a second electrically conductive...
US-9,589,938 Semiconductor device including an embedded surface mount device and method of forming the same
Embodiments of the present disclosure include devices and methods of forming the same. An embodiment is a device including a solder resist coating over a first...
US-9,589,937 Semiconductor cooling method and method of heat dissipation
The invention provides a semiconductor cooling method that comprises: providing two wafers which require to be treated by a mixed bonding process, wherein each...
US-9,589,936 3D integration of fanout wafer level packages
Fanout wafer level packages (FOWLPs) and methods of formation are described. In an embodiment, a package includes a first routing layer, a first die on a top...
US-9,589,935 Package apparatus and manufacturing method thereof
A package apparatus includes a first package module, a second package module and multiple conductive elements. The first package module includes a first molding...
US-9,589,934 Method for interconnecting stacked semiconductor devices
A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The...
US-9,589,933 Methods of processing wafer-level assemblies to reduce warpage, and related assemblies
Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in...
US-9,589,932 Interconnect structures for wafer level package and methods of forming same
Representative methods are disclosed for fabricating device packages having a plurality of dies, a molding compound extending along sidewalls of the plurality...
US-9,589,931 Bundled memory and manufacture method for a bundled memory with an external input/output bus
A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first...
US-9,589,930 Semiconductor package including stepwise stacked chips
A semiconductor package comprises a package substrate; a first chip stack and a second chip stack mounted side by side on the package substrate, wherein the...
US-9,589,929 Method for fabricating stack die package
In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are...
US-9,589,928 Combined QFN and QFP semiconductor package
A semiconductor package includes a first lead frame type having a first type of package leads and a pre-molded portion, and a second lead frame type having a...
US-9,589,927 Packaged RF amplifier devices with grounded isolation structures and methods of manufacture thereof
An embodiment of a packaged RF amplifier device includes a device substrate, a transistor die coupled to the device substrate, and an isolation structure...
US-9,589,926 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device that includes: preparing a pair of substrates that respectively include a device structure on one primary...
US-9,589,925 Method for bonding with a silver paste
Disclosed is a method for bonding with a silver paste, the method including: coating a silver paste on a semiconductor device or a substrate, the silver paste...
US-9,589,924 Semiconductor structure and method of manufacturing the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate comprising a recess portion filled...
US-9,589,923 Method of manufacturing semiconductor device
Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding...
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