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Patent # Description
US-9,589,872 Integrated dual power converter package having internal driver IC
An integrated dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a...
US-9,589,871 Semiconductor package structure and method for manufacturing the same
The present disclosure relates to a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a...
US-9,589,870 Semiconductor device and lead frame used for the same
A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an...
US-9,589,869 Packaging solutions for devices and systems comprising lateral GaN power transistors
Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a...
US-9,589,868 Packaging solutions for devices and systems comprising lateral GaN power transistors
Packaging solutions for large area, GaN die comprising one or more lateral GaN power transistor devices and systems are disclosed. Packaging assemblies comprise...
US-9,589,867 Semiconductor device
A semiconductor device includes: a semiconductor element having a gate and source electrodes; an insulating substrate which is provided with an insulating...
US-9,589,866 Bridge interconnect with air gap in package assembly
Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package...
US-9,589,865 Power amplifier die having multiple amplifiers
An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a semiconductor die having second stages of...
US-9,589,864 Substrate with embedded sintered heat spreader and process for making the same
The present disclosure relates to a substrate with an embedded sintered heat spreader and a process for making the same. According to an exemplary process, at...
US-9,589,863 Power module and thermal interface structure thereof
A power module and a thermal interface structure are provided herein. The thermal interface structure includes: a base and a plurality of filler particles...
US-9,589,862 Interconnect structures and methods of forming same
Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is a method of forming an...
US-9,589,861 Semiconductor packaging having warpage control and methods of forming same
An embodiment method for forming a semiconductor device package comprises bonding a first die to a package substrate and forming a molding compound over the...
US-9,589,859 Semiconductor arrangement, method for producing a number of chip assemblies and method for producing a...
A semiconductor arrangement includes a plurality of chip assemblies, each of which includes a semiconductor chip having a semiconductor body with a top side and...
US-9,589,857 Interposer test structures and methods
An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and...
US-9,589,856 Automatically adjusting baking process for low-k dielectric material
A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the...
US-9,589,855 Method for manufacturing X-ray flat panel detector and X-ray flat panel detector TFT array substrate
A common interconnect ring is provided at a periphery of a portion used to form a TFT array of an X-ray flat panel detector, and an X-ray flat panel detector...
US-9,589,854 Alignment monitoring structure and alignment monitoring method for semiconductor devices
The present disclosure provides in various aspects an alignment monitoring structure and method for monitoring the alignment between a target gate conductor and...
US-9,589,853 Method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber
A method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber comprises supporting the substrate on a support surface of a...
US-9,589,852 Electrostatic phosphor coating systems and methods for light emitting structures and packaged light emitting...
Methods are disclosed including applying a layer of binder material onto an LED structure. A luminescent solution including an optical material suspended in a...
US-9,589,851 Dipole-based contact structure to reduce metal-semiconductor contact resistance in MOSFETs
A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at...
US-9,589,850 Method for controlled recessing of materials in cavities in IC devices
Controlled recessing of materials in cavities and resulting devices are disclosed. Embodiments include providing a dielectric layer over first-type and...
US-9,589,849 Methods of modulating strain in PFET and NFET FinFET semiconductor devices
One illustrative method disclosed herein includes, among other things, forming a plurality of initial fins that have the same initial axial length and the same...
US-9,589,848 FinFET structures having silicon germanium and silicon channels
Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and...
US-9,589,847 Metal layer tip to tip short
Techniques relate to forming an integrated circuit. Trench contacts are formed on top of at least one source and drain of an intermediate structure. An...
US-9,589,846 Method of forming semiconductor device
A method for forming a semiconductor device is provided. First, a dielectric layer is provided on a substrate, wherein a first recess and a second recess are...
US-9,589,845 Fin cut enabling single diffusion breaks
A method is provided for forming a fin cut that enables a single diffusion break in very dense CMOS structures formed using bulk semiconductor substrates. A...
US-9,589,844 Electronic die singulation method
In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a carrier substrate with the back layer adjacent the carrier...
US-9,589,843 Method for manufacturing a semiconductor device
The manufacturing efficiency of a semiconductor device is improved. A method for manufacturing a semiconductor device includes a step of sealing a semiconductor...
US-9,589,842 Semiconductor package and method of fabricating the same
A method of fabricating a semiconductor package is disclosed. The method includes disposing semiconductor chips on a support substrate, forming a protection...
US-9,589,841 Electronic package and fabrication method thereof
A method for fabricating an electronic package is provided, including the steps of: providing at least a packaging structure, wherein the packaging structure...
US-9,589,840 Semiconductor package and manufacturing method thereof
The present disclosure relates to a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor element...
US-9,589,839 Method of reducing control gate electrode curvature in three-dimensional memory devices
Corner rounding of electrically conductive layers in a replacement electrode integration scheme can be alleviated by employing compositionally modulated...
US-9,589,838 Contact structure of semiconductor device
The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a...
US-9,589,837 Electrode manufacturing method, fuse device and manufacturing method therefor
The present disclosure relates to an electrode manufacturing method, and a fuse device and manufacturing method therefor. The fuse device includes a fuse...
US-9,589,836 Methods of forming ruthenium conductive structures in a metallization layer
One illustrative method disclosed herein includes, among other things, forming a first conductive structure and a second conductive structure that is...
US-9,589,835 Method for forming tungsten film having low resistivity, low roughness and high reflectivity
Top-down methods of increasing reflectivity of tungsten films to form films having high reflectivity, low resistivity and low roughness are provided. The...
US-9,589,834 Array substrate and manufacturing method thereof, and display device
An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes a thin film transistor on a base substrate,...
US-9,589,833 Preventing leakage inside air-gap spacer during contact formation
Techniques for preventing leakage of contact material into air-gap spacers during contact formation. For example, a method comprises forming a contact trench on...
US-9,589,832 Maintaining mask integrity to form openings in wafers
One or more openings in an organic mask layer deposited on a first insulating layer over a substrate are formed. One or more openings in the first insulating...
US-9,589,831 Mechanisms for forming radio frequency (RF) area of integrated circuit structure
A method for forming a radio frequency area of an integrated circuit are provided. The method includes forming a buried oxide layer over a substrate, and an...
US-9,589,830 Method for transferring a useful layer
A method for transferring a useful layer onto a support includes the following processes: formation of a fragilization plane through the implantation of light...
US-9,589,829 FinFET device including silicon oxycarbon isolation structure
A method includes forming a plurality of fins on a semiconductor substrate by defining a plurality of trenches in the substrate. A first insulating material...
US-9,589,828 Method for photolithography-free self-aligned reverse active etch
A layer of partially planarized organosilicate (DUO) is spin-coated onto a layer of high density plasma (HDP) oxide on a silicon wafer after the shallow trench...
US-9,589,827 Shallow trench isolation regions made from crystalline oxides
A method of manufacturing a semiconductor device that involves etching a trench in a semiconductor substrate, epitaxially growing a crystalline structure in the...
US-9,589,826 Sample holder
A sample holder includes a substrate composed of ceramics, having a sample holding surface provided in an upper face thereof; a supporting member composed of...
US-9,589,825 Glass substrate transfer system and robot arm thereof
A glass substrate transfer system and a robot arm thereof are provided. The robot arm includes: a substrate fork, a moving assembly and a vacuum chuck. The...
US-9,589,824 Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device is provided. The method includes a process of applying liquid to one surface of a support substrate; a process...
US-9,589,823 Mounting table and plasma processing apparatus
A mounting table includes an electrostatic chuck, a base, and a cylindrical sleeve. The electrostatic chuck has a top surface to be exposed to plasma and a...
US-9,589,822 Substrate transfer method with a second positioning step
A substrate transfer method includes a step of placing a first and a second substrate on a first and a second alignment part which are arranged to be vertically...
US-9,589,821 Article transport facility and maintenance operation method of article transport facility
A supporting portion of an article transport device supports a position detection device for detecting the position of a detection target object. A control...
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