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Patent # Description
US-9,589,669 Semiconductor devices and semiconductor systems
A semiconductor system and semiconductor device may be provided. The semiconductor system may include a first semiconductor device configured to generate a test...
US-9,589,668 Semiconductor memory device for performing test operation of circuits related to repair scheme and operating...
A semiconductor memory device includes a memory cell array including a plurality of word lines; a repair fuse section programmed with one or more repair-target...
US-9,589,667 Gate drive circuit and drive method for the same
A gate drive circuit is disclosed. The drive circuit includes M cascaded shift registers, where M is a natural number, and a clock controller configured to...
US-9,589,666 Amorphous silicon gate driving circuit, flat panel sensor and display device
An amorphous silicon gate driving circuit includes multiple cascaded shift registers. Each of the shift registers includes a shift register unit, which contains...
US-9,589,664 Gate driver, array substrate, display panel and display device
The present disclosure discloses a gate driver, an array substrate, a display panel and a display device so as to address problems in the gate driver that some...
US-9,589,663 OTP memory capable of performing multi-programming and semiconductor memory device including the same
A one-time programmable (OTP) memory capable of performing a multi-programming and a semiconductor memory device including the OTP memory are disclosed. The OTP...
US-9,589,662 Resistive memory device with variable cell current amplification
A resistive memory device includes a resistive memory cell whose resistance value varies based on a logic value of data stored therein, a current amplification...
US-9,589,661 Method of programming memory device and method of reading data of memory device including the same
A method of programming target memory cells of a nonvolatile memory device includes; programming the target memory cells using an incrementally adjusted program...
US-9,589,660 Semiconductor pillars charged in read operation
A memory device includes a word line above a semiconductor substrate, a semiconductor pillar extending through the word line in a direction crossing a surface...
US-9,589,659 Pre-compensation of memory threshold voltage
Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target...
US-9,589,658 Disturb free bitcell and array
Approaches for a memory including a cell array are provided. The memory includes a first device of the cell array which is connected to a bitline and a node and...
US-9,589,657 Internal power supply voltage auxiliary circuit, semiconductor memory device and semiconductor device
The disclosure provides an internal power supply voltage auxiliary circuit for an internal power supply voltage generating circuit, wherein the internal power...
US-9,589,656 Voltage generation circuit which is capable of executing high-speed boost operation
According to one embodiment, a voltage generation circuit includes a first boost circuit, a voltage division circuit, a first detection circuit, a capacitor and...
US-9,589,655 Fast soft data by detecting leakage current and sensing time
Systems and methods for low latency acquisition of soft data from a memory cell based on a sensing time and/or a leakage current are described. In one...
US-9,589,654 Rank determination of circuits with distinct current carrying capabilities
Technologies are generally provided for methods and circuitry to rank a large number of cells in a timeframe of about one sense cycle. In some examples, an...
US-9,589,653 Creating default states for non-volatile memory elements
A circuit has a wordline with an NVM element utilizing a first FET coupled to bitline true and a second FET coupled to bitline complement. A NFET coupled to the...
US-9,589,652 Asymmetric pass field-effect transistor for non-volatile memory
A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric...
US-9,589,651 Semiconductor memory device and controlling method thereof
A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of charge accumulation type memory cells; and a...
US-9,589,650 Circuit for erasing data
A circuit for erasing data includes: a high voltage generation unit, adapted for generating an erasing signal; a first control unit, adapted for modifying the...
US-9,589,648 Semiconductor memory device
A semiconductor memory device includes a memory string on a well, the memory string including a memory cell connected in series between first and second select...
US-9,589,647 Semiconductor device with improved programming reliability
A semiconductor memory device includes a memory string including a first cells portion and a second cells portion each including a multiple of memory cells, the...
US-9,589,646 Page buffer circuit having bias voltage application unit and operating method of same
A page buffer circuit includes a plurality of page buffers including a first page buffer. The first page buffer is configured to load input data of the first...
US-9,589,645 Block refresh to adapt to new die trim settings
Systems, apparatuses, and methods may be provided that adapt to trim set advancement. Trim set advancement may be a change in trim sets over time. A cell of a...
US-9,589,644 Reducing programming disturbance in memory devices
Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a...
US-9,589,643 Nonvolatile memory device including multi-plane
A nonvolatile memory device includes a memory cell array including cell strings stacked in a direction orthogonal to a substrate and including a first substring...
US-9,589,642 Level shifter and decoder for memory
A level shifter receiving an input with a relatively narrow voltage range and provides an output with a relatively wide voltage range. The level shifter...
US-9,589,641 Semiconductor memory device
A semiconductor memory device includes a first page buffer block and a second page buffer block corresponding to a first memory bank and a second memory bank,...
US-9,589,640 Data storage device including nonvolatile memory device and operating method thereof
A method of a operating a data storage device including a nonvolatile memory device and a memory controller is provided. The method includes reading a first...
US-9,589,639 Multiple FET non-volatile memory with default logical state
A memory array has a NVM element with a plurality of FETs. A first set of FETs of the plurality of FETs is coupled to a bitline true of the memory array. The...
US-9,589,638 Semiconductor device and method of driving semiconductor device
A first potential and a second potential lower than the first potential are applied to a first end of a memory gate electrode part of the nonvolatile memory and...
US-9,589,637 Storage element with storage and clock tree monitoring circuit and methods therefor
A storage element with monitoring circuit, comprising a previous state information storage element configured to record a previous state of a monitored state...
US-9,589,636 Method, system and device for complementary non-volatile memory device operation
Disclosed are methods, systems and devices for operation of dual non-volatile memory devices. In one aspect, a pair of non-volatile memory device coupled in...
US-9,589,635 Semiconductor device with a stoichiometric gradient
A device that includes a semiconductor device and a contact electrode with a first side that is opposite a second side. The first side abuts the semiconductor...
US-9,589,634 Techniques to mitigate bias drift for a memory device
Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is...
US-9,589,633 Memory devices and related methods
A resistive memory device. Implementations may include an array of memory cells including resistive memory elements which are coupled to isolation transistors...
US-9,589,632 Resistive memory device including column decoder and method of performing a bidirectional driving operation and...
A resistive memory device includes a column decoder having a first switch unit, including at least one pair of switches arranged in correspondence to each of a...
US-9,589,631 Ultrafast quench based nonvolatile bistable device
The invention refers to an ultrafast quench based nonvolatile bistable device which consists of an active material on a passive or active substrate which...
US-9,589,630 Low voltage current reference generator for a sensing amplifier
The invention comprises a non-volatile memory device with a sensing amplifier that includes a current mirror comprising a pair of resistors.
US-9,589,629 Semiconductor memory with data line capacitive coupling
A method of accessing a semiconductor memory includes operations as follows. A first voltage is received at a first data line, and a second voltage is received...
US-9,589,628 Semiconductor device performing refresh operation and method for driving the same
A semiconductor device includes a first memory block, a second memory block, a first refresh control block for generating a first block control signal and a...
US-9,589,627 Methods and devices for a DDR memory driver using a voltage translation capacitor
Embodiments relate to systems, methods and computer readable media to enable design and creation of memory driver circuitry using a voltage translation...
US-9,589,626 Single-ended memory signal equalization at power up
An apparatus having a first circuit and a second circuit. The first circuit may be configured to buffer an input signal received as a single-ended signal from a...
US-9,589,625 Method of operating memory device and refresh method of the same
A method of operating a memory device may include: providing a first power supply voltage to a sense amplifier during a first time interval, the first time...
US-9,589,624 Semiconductor device, memory access control method, and semiconductor device system
In a semiconductor device in accordance with one embodiment, a memory access control unit counts the number of addresses accessed by burst access to each...
US-9,589,623 Word shift static random access memory (WS-SRAM)
Word shift static random access memory (WS-SRAM) cell, word shift static random access memory (WS-SRAM) and method using the same employ dynamic storage mode...
US-9,589,622 Method of writing to a spin torque magnetic random access memory
Circuitry and methods provide an increased tunnel barrier endurance (lifetime) previously shortened by dielectric breakdown by providing a charging pulses of...
US-9,589,621 Resistance change memory
A resistance change memory includes a memory cell array comprising memory cells including magnetic tunnel junction (MTJ) elements; a write and read circuit...
US-9,589,620 Destructive reads from spin transfer torque memory under read-write conditions
Systems, apparatuses and methods may provide for detecting a read-write condition in which a read operation from a location in magnetoresistive memory such as...
US-9,589,619 Spin-orbit-torque magnetoresistive random access memory with voltage-controlled anisotropy
Methods and apparatus relating to spin-orbit-torque magnetoresistive random access memory with voltage-controlled anisotropy are disclosed. In an example,...
US-9,589,618 Unidirectional spin torque transfer magnetic memory cell structure
Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices...
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