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Patent # Description
US-9,595,536 Standard cell library that includes 13-CPP and 17-CPP D flip-flop cells, with DFM-optimized M0 cuts and V0...
A library of a DFM-improved standard logic cells that avoid pattern-degrading configurations in the M0 and/or V0 layer(s), and includes 13-CPP and 17-CPP D...
US-9,595,535 Integration of word line switches with word line contact via structures
Word line switches in a word line decoder circuitry for a three-dimensional memory device can be formed as vertical field effect transistors overlying contact...
US-9,595,534 U-shaped common-body type cell string
A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped...
US-9,595,533 Memory array having connections going through control gates
Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus...
US-9,595,532 Semiconductor device and manufacturing method thereof
An improvement is achieved in the performance of a semiconductor device having a nonvolatile memory. A memory cell of the nonvolatile memory includes a control...
US-9,595,531 Aluminum oxide landing layer for conductive channels for a three dimensional circuit device
A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a...
US-9,595,530 Methods and apparatus for vertical bit line structures in three-dimensional nonvolatile memory
A method is provided that includes forming a first vertical bit line disposed in a first direction above a substrate, forming a first word line disposed in a...
US-9,595,529 Fuse cell circuit, fuse cell array and memory device including the same
A fuse cell circuit may include a bit line, a first fuse transistor having first and second program states, a first select transistor coupled between one...
US-9,595,528 Semiconductor device and method of manufacturing the same
To prevent contact plugs formed to sandwich an abutting portion between gate electrodes, from being short-circuited via a void formed inside an insulating film...
US-9,595,527 Coaxial carbon nanotube capacitor for eDRAM
A deep trench (DT) opening is provided in a semiconductor substrate and then conducting carbon nanotubes are formed within the DT. Each conducting carbon...
US-9,595,526 Multi-die fine grain integrated voltage regulation
A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more...
US-9,595,525 Semiconductor device including nanowire transistors with hybrid channels
A semiconductor device is provided that includes an n-type field effect transistor including a plurality of vertically stacked silicon-containing nanowires...
US-9,595,524 FinFET source-drain merged by silicide-based material
A method includes conducting a laser-based anneal treatment on a metal layer positioned above and in direct contact with a top portion of a silicon cap layer...
US-9,595,523 Semiconductor integrated circuit devices
A semiconductor integrated circuit device may include a standard cell region on a surface of a substrate and a first active region on the surface of the...
US-9,595,522 Semiconductor device with a dislocation structure and method of forming the same
A semiconductor device with bi-layer dislocation and method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method...
US-9,595,521 Capacitive device
A method of manufacturing a capacitive device. The method includes doping a substrate to form a well region, forming M shoulder portions and (M-1) trenches in...
US-9,595,520 IGBT with built-in diode and manufacturing method therefor
An insulated gate bipolar translator (IGBT) with a built-in diode and a manufacturing method thereof are provided. The IGBT comprises: a semiconductor substrate...
US-9,595,519 Combination metal oxide semi-conductor field effect transistor (MOSFET) and junction field effect transistor...
Systems and methods for controlling current or mitigating electromagnetic or radiation interference effects using a combination of a metal-oxide semiconductor...
US-9,595,518 Fin-type metal-semiconductor resistors and fabrication methods thereof
Fabrication methods and structure include: providing a wafer with at least one fin extended above a substrate in a first region, and at least one fin extended...
US-9,595,517 Semiconductor device employing trenches for active gate and isolation
A semiconductor device includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer...
US-9,595,516 Semiconductor devices and arrangements including dummy gates for electrostatic discharge protection
A semiconductor device and device arrangement including a plurality of semiconductor regions of different conductivity types and a plurality of gates which form...
US-9,595,515 Semiconductor chip including integrated circuit defined within dynamic array section
A semiconductor chip includes four linear-shaped conductive structures that each form a gate electrode of corresponding transistor of a first transistor type...
US-9,595,514 Package with SoC and integrated memory
A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The...
US-9,595,513 Proximity coupling of interconnect packaging systems and methods
Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed...
US-9,595,512 Passive component integrated with semiconductor device in semiconductor package
According to one exemplary embodiment, a semiconductor package includes a substrate having lower and upper surfaces. The semiconductor package further includes...
US-9,595,511 Microelectronic packages and assemblies with improved flyby signaling operation
A microelectronic unit includes microelectronic elements having memory storage arrays. First terminals and second terminals at a surface of the microelectronic...
US-9,595,510 Structure and formation method for chip package
Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely...
US-9,595,509 Stacked microelectronic package assemblies and methods for the fabrication thereof
Stacked microelectronic package assemblies are provided, as are methods for producing stacked microelectronic package assemblies. In one embodiment, the stacked...
US-9,595,508 Voltage droop mitigation in 3D chip system
The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies...
US-9,595,507 Semiconductor device and method of manufacturing the same
According to one embodiment, a semiconductor device includes a laminate including a plurality of semiconductor chips and having a first width, at least part of...
US-9,595,506 Packages with thermal management features for reduced thermal crosstalk and methods of forming same
An embodiment package includes a first die stack on a surface of a package component, a second die stack on the surface of the package component, and a contour...
US-9,595,505 Thermally-enhanced three dimensional system-in-packages and methods for the fabrication thereof
Embodiments of three dimensional (3D) System-in-Package (SiPs) and methods for producing 3D SiPs having improved heat dissipation capabilities are provided. In...
US-9,595,504 Methods and systems for releasably attaching support members to microfeature workpieces
Methods and apparatuses for releasably attaching support members to microfeature workpieces to support members are disclosed herein. In one embodiment, for...
US-9,595,503 Dual lead frame semiconductor package and method of manufacture
A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has...
US-9,595,502 Spring contact for semiconductor chip
A semiconductor assembly is described. In accordance with one example of the invention, the semiconductor assembly comprises a semiconductor body, a top main...
US-9,595,501 Wire bonded electronic devices to round wire
A disclosed circuit arrangement includes a flexible substrate. A layer of pressure sensitive adhesive (PSA) is directly adhered to a first major surface of the...
US-9,595,500 Semiconductor device
A semiconductor device includes: a semiconductor chip having a switching element and multiple pads electrically connected to the switching element; and multiple...
US-9,595,499 Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages...
A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and...
US-9,595,498 Semiconductor memory device having pads
A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor...
US-9,595,497 Display with low reflectivity alignment structures
A display may have a thin-film transistor layer formed from a layer of thin-film, transistor circuitry on a substrate. The thin-film transistor layer may...
US-9,595,496 Integrated device package comprising silicon bridge in an encapsulation layer
Some novel features pertain to an integrated device package that includes an encapsulation portion and a redistribution portion. The encapsulation portion...
US-9,595,495 Multi-level signaling for on-package chip-to-chip interconnect through silicon bridge
One embodiment relates to an apparatus for data communication between at least two in-package semiconductor dies. On the first semiconductor die in a package, a...
US-9,595,494 Semiconductor package with high density die to die connection and method of making the same
A semiconductor package according to some examples of the disclosure may include a substrate having a bridge embedded in the substrate, a first and second die...
US-9,595,493 Reducing liner corrosion during metallization of semiconductor devices
Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a...
US-9,595,492 Device manufacture and packaging method thereof
Some embodiments of the present disclosure provide a semiconductive device. The semiconductive device includes a first conductive layer and a second conductive...
US-9,595,491 Apparatus for manufacturing semiconductor device and the semiconductor device
An apparatus for a manufacturing semiconductor device including a plate member and a joint member. The apparatus includes a plate-type tool having the plate...
US-9,595,490 3D system-level packaging methods and structures
A 3D system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement...
US-9,595,489 Semiconductor package with bonding wires of reduced loop inductance
A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged...
US-9,595,488 Semiconductor device
A semiconductor device according to one embodiment of the present invention includes a semiconductor element, an island having a surface on which the...
US-9,595,487 Circuit arrangement and method for manufacturing the same
Various embodiments may provide a circuit arrangement. The circuit arrangement may include a carrier having at least one electrically conductive line; a...
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