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Patent # Description
US-9,602,137 Transmitting apparatus and interleaving method thereof
A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC...
US-9,602,136 Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 4/15 and...
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first...
US-9,602,135 Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 5/15 and...
A bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length...
US-9,602,134 Operating method of error correction code decoder and memory controller including the error correction code decoder
An operating method of an ECC decoder includes receiving first chunk data and second chunk data from a nonvolatile memory device, the second chunk data...
US-9,602,133 System and method for boost floor mitigation
A method for boost floor mitigation during a decoding operation performed by a decoder is disclosed herein. The method includes: monitoring for a floor error...
US-9,602,132 Transmitter, encoding apparatus, receiver, and decoding apparatus
An encoding apparatus includes a dividing unit that divides an input signal bit sequence into data blocks and an encoding unit that applies error correction...
US-9,602,131 Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and...
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first...
US-9,602,130 System and method for matching a regular expression or combination of characters
A system and method for comparing a character from a search space simultaneously to each of a set of search characters. The set of search characters may...
US-9,602,129 Compactly storing geodetic points
Mechanisms are provided for the compact storage of geographical geometries as a collection of points, where individual points are encoded as binary/ternary...
US-9,602,128 Split gain shape vector coding
The invention relates to an encoder and a decoder and methods therein for supporting split gain shape vector encoding and decoding. The method performed by an...
US-9,602,127 Devices and methods for pyramid stream encoding
Devices and methods of reducing quantization noise using a pyramid stream encoder are generally described. Groups of D digital symbols are iteratively computed...
US-9,602,126 Sigma-delta analog-to-digital converter
The present invention is related to a sigma-delta analog-to-digital converter (ADC). It further relates to a method for designing and manufacturing a...
US-9,602,125 Wideband InP digital-to-analog converter integrated with a SiGe clock distribution network
A digital-to-analog converter (DAC) including a DAC core circuit having a plurality of input lines each being responsive to a digital bit input signal and an...
US-9,602,124 A/D conversion device having level shifter circuit
An A/D conversion device includes: a level shifter circuit configured to level-shift an analog voltage of an input voltage signal to generate a conversion...
US-9,602,123 Cognitive signal converter
A cognitive signal converter adapted to produce a digital output signal based on an analog input signal comprises an analog-to-digital converter (ADC) and a...
US-9,602,122 Process variable measurement noise diagnostic
A process variable transmitter, includes an analog-to-digital (A/D) converter that receives a sensor signal provided by a sensor that senses a process variable...
US-9,602,121 Background estimation of comparator offset of an analog-to-digital converter
A pipeline analog-to-digital converter (ADC) converts an analog input signal over several stages, where a stage generates a residue for the subsequent stage to...
US-9,602,120 Analog to digital converter with digital reference voltage signal
An analog to digital converter contain a plurality of comparators, each having a plurality of positive input voltage transistors and a plurality of negative...
US-9,602,119 Gain calibration by applying a portion of an input voltage to voltage associated with a capacitor array
Various aspects facilitate gain adjustment associated with an analog to digital converter. A capacitor array comprises a plurality binary-weighted capacitors...
US-9,602,118 Amplifier sharing technique for power reduction in analog-to-digital converter
A dual delta-sigma modulator includes a first modulator, a second modulator, and a shared amplifier coupled to the first and second modulators. The first...
US-9,602,117 Detection device, sensor, electronic apparatus, and moving object
A detection device includes a driving circuit and a detection circuit. The detection circuit includes first and second electric charge-voltage conversion...
US-9,602,116 Interleaved successive approximation register analog to digital converter
In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there...
US-9,602,115 Method and apparatus for multi-rate clock generation
A method and device for generating a multi-rate clock signal using a ring voltage-controlled oscillator based phase-locked loop is provided. The device includes...
US-9,602,114 Phase-locked loop with multiple degrees of freedom and its design and fabrication method
A design method for a phase-locked loop comprises: a controlled-frequency oscillator; a phase comparator, to determine a phase difference between an output...
US-9,602,113 Fast frequency throttling and re-locking technique for phase-locked loops
Certain aspects of the present disclosure support a method and apparatus for fast frequency throttling and re-locking in a phase-locked loop (PLL) device....
US-9,602,112 Clock delay detecting circuit and semiconductor apparatus using the same
Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay...
US-9,602,111 Delay locked loop (DLL) locked to a programmable phase
An asynchronous digital logic is used to provide a pulse. A pulse train is filtered to determine an analog measurement based at least in part on the duty cycle...
US-9,602,110 Oscillator amplifier biasing technique to reduce frequency pulling
An oscillator amplifier biasing technique configures an oscillator amplifier to operate at a bias point causing loading on a tank circuit to have reduced or...
US-9,602,109 Method and circuit configuration for determining position minus time
A circuit configuration for a data processing system for predicting a coordinate for at least one operation to be carried out is provided, the prediction being...
US-9,602,108 Lut cascading circuit
In an example, a LUT for a programmable integrated circuit (IC) includes a plurality of input terminals, and a cascading input coupled to at least one other LUT...
US-9,602,107 Reset selection cell to mitigate initialization time
A circuit includes a state capture device to capture a logic state of a reset selection cell in response to a logic state input. A cell reset node defines a...
US-9,602,106 Methods for optimizing circuit performance via configurable clock skews
An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals...
US-9,602,105 Performance-on-demand IC chip design in integrated-injection logic
A circuit comprising a first injection BJT in a common-base configuration and configured to output a first injection current at its collector. A first...
US-9,602,104 Output buffer with offset cancellation structure and offset cancellation method using the same
An output buffer with an offset cancellation structure for an LCD source driver includes an operational amplifier, for driving an output signal of the output...
US-9,602,103 Spin wave device and logic circuit using spin wave device
As a technique for attaining a reduction in power consumption, there is a technique for reducing power consumption using a spin wave. No specific proposal...
US-9,602,102 Magnetic logic device, magnetic logic circuit, and magnetic memory
One embodiment provides a magnetic logic device including: a first conductive thin wire; a second conductive thin wire; and a third conductive thin wire that...
US-9,602,101 Integrated device with auto configuration
A method for controlling a configuration in an integrated circuit device with at least one controllable input/output port having a data output driver, a data...
US-9,602,100 Downhole measurement tool having a regulated voltage power supply and method of use thereof
The invention relates generally to downhole measurement tools having a regulated voltage power supply and methods of use thereof. The downhole measurement tools...
US-9,602,099 Adaptive duo-gate MOSFET
An adaptive duo-gate MOSFET includes a trench MOSFET and an adaptive element. The trench MOSFET includes a source, a drain, a first gate, a second gate, and a...
US-9,602,098 RF switch with bypass topology
An RF signal switch circuit that allows connection of any of N radio frequency (RF) input terminals to a switch output port, either in an in-circuit mode or in...
US-9,602,097 System and method having a first and a second operating mode for driving an electronic switch
An electronic switch is connected in series with a load dependent on an input signal. The electronic switch is operated in a first operation mode for a first...
US-9,602,096 Power electronic device with improved efficiency and electromagnetic radiation characteristics
A power electronic device includes first and second electronic switches, each integrated on a package having a low parasitic inductance, a supply terminal and a...
US-9,602,095 Multiplexer circuit, computer-readable recording medium having stored therein program for designing multiplexer...
In a multiplexer circuit which loads N data segments (N is an integer of N<M) led by an arbitrary data segment from a first register storing M data segments...
US-9,602,094 Decoding circuit and method of decoding signal
A decoding circuit may include a section information generation unit suitable for generating section information corresponding to a section in which an input...
US-9,602,093 Zero-crossing voltage detection circuit and method thereof
A zero-crossing voltage detection circuit for detecting a phase voltage of a converter includes a comparator, a first transistor and a second transistor. The...
US-9,602,092 Dynamic margin tuning for controlling custom circuits and memories
Embodiments of a method that may allow for selectively tuning a delay of individual logic paths within a custom circuit or memory are disclosed. Circuitry may...
US-9,602,091 Low phase shift, high frequency attenuator
A wideband RF attenuator circuit that has a reduced impact on the phase of an applied signal when switched between an attenuation state and a non-attenuating...
US-9,602,090 Skew adjustment apparatus
First to N-th selection signals each instantaneously having a first logic level when representing selection and a second logic level when representing...
US-9,602,089 Amplifying device and offset voltage correction method
A state wherein offset voltage is reduced can be maintained regardless of environmental fluctuation. A differential amplification unit has differential pair...
US-9,602,088 Ultra-low power comparator with sampling control loop adjusting frequency and/or sample aperture window
Methods and apparatus for minimizing average quiescent current for a desire voltage error in a comparator are disclosed. An example method includes receiving a...
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