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Patent # Description
US-9,601,531 Wafer-level packaging structure for image sensors with packaging cover dike structures corresponding to scribe...
A wafer level packaging structure for image sensors and a wafer level packaging method for image sensors are provided. The wafer level packaging structure...
US-9,601,530 Dual active layer semiconductor device and method of manufacturing the same
Some embodiments include a semiconductor device. The semiconductor device includes a transistor having a gate metal layer, a transistor composite active layer,...
US-9,601,529 Light absorption and filtering properties of vertically oriented semiconductor nano wires
A nanowire array is described herein. The nanowire array comprises a substrate and a plurality of nanowires extending essentially vertically from the substrate;...
US-9,601,528 Manufacturing method of array substrate
The present invention provides a manufacturing method of an array substrate, comprising steps of: forming a gate and a gate line on a substrate; forming a gate...
US-9,601,527 Thin film transistor array substrate, organic light-emitting display apparatus, and method of manufacturing the...
A thin film transistor array substrate includes a thin film transistor including a first gate electrode, an active layer, a source electrode, and a drain...
US-9,601,526 Display device and manufacturing method thereof
A display device is provided. A substrate includes a thin film transistor. A pixel electrode is connected to the thin film transistor. A common electrode is...
US-9,601,525 Semiconductor device
Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a...
US-9,601,524 Display device and method of manufacturing the same
A display device is disclosed. In one aspect, the device includes a plurality of pixels. Each of the pixels includes a first thin-film transistor (TFT) formed...
US-9,601,523 Dual gate TFT substrate structure utilizing COA skill
The present invention provides a dual gate TFT substrate structure utilizing COA skill, comprising a substrate (1), a bottom gate (2) positioned on the...
US-9,601,521 Liquid crystal display
A liquid crystal display including a plurality of pixels that display an image, each pixel includes a thin film transistor that includes a gate electrode, a...
US-9,601,520 Thin film transistor array panel and display device including the same
Exemplary embodiments of the present invention relate to a panel and a display device including the same, the panel including a substrate, a signal line...
US-9,601,519 Thin film transistor and display panel including the same
A thin film transistor is provided, which includes a gate electrode on a substrate; a channel layer overlapping the gate electrode; a dielectric layer between...
US-9,601,518 Thin film transistor display panel and method for manufacturing the same
A thin film transistor display panel including: a first insulating substrate; a first semiconductor disposed between the first insulating substrate and a first...
US-9,601,517 Hybrid pixel control circuits for light-emitting diode display
An electronic device may include a display. The display may be formed by an array of light-emitting diodes mounted to the surface of a substrate. The...
US-9,601,516 Semiconductor device and manufacturing method thereof
The semiconductor device includes a driver circuit portion including a driver circuit and a pixel portion including a pixel. The pixel includes a gate electrode...
US-9,601,515 Semiconductor device and manufacturing method thereof
A high reliability semiconductor display device is provided. A semiconductor layer in the semiconductor display device has a channel forming region, an LDD...
US-9,601,514 Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy
Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin...
US-9,601,513 Subsurface wires of integrated chip and methods of forming
Various embodiments include methods and integrated circuit structures. One method includes masking a structure with a mask to cover at least a portion of the...
US-9,601,512 SOI-based semiconductor device with dynamic threshold voltage
A semiconductor device includes a semiconductor substrate, an insulating layer on a top surface of the substrate, and a first semiconductor transistor on the...
US-9,601,511 Low leakage dual STI integrated circuit including FDSOI transistors
An integrated circuit, including: a UTBOX layer; a first cell, including: FDSOI transistors; a first STI separating the transistors; a first ground plane...
US-9,601,510 Semiconductor device with six transistors forming a NAND circuit
A semiconductor device has a small area and constitutes a CMOS 3-input NAND circuit by using surrounding gate transistors (SGTs) that are vertical transistors....
US-9,601,509 Semiconductor device having slit between stacks and manufacturing method of the same
The present disclosure may provide a semiconductor device having a three-dimensional memory device with improved performance and reliability. The device may...
US-9,601,508 Blocking oxide in memory opening integration scheme for three-dimensional memory structure
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the...
US-9,601,507 Semiconductor device and method of manufacturing semiconductor device
According to one embodiment, a semiconductor device includes an insulating layer provided on a semiconductor substrate, an opening provided on the insulating...
US-9,601,506 Semiconductor structure and method for manufacturing the same
A semiconductor structure is provided. The semiconductor structure comprises a substrate, stacks, a blocking layer-trapping layer-tunneling layer structure,...
US-9,601,505 Semiconductor device
A semiconductor device includes a first selection gate insulating film surrounding a first pillar-shaped semiconductor layer, a first selection gate surrounding...
US-9,601,504 Semiconductor device and method of manufacturing the same
A semiconductor device according to an embodiment of the invention includes a pipe channel layer including a first portion and a second portion protruding from...
US-9,601,503 Nonvolatile semiconductor memory device and method for manufacturing same
A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of...
US-9,601,502 Multiheight contact via structures for a multilevel interconnect structure
A recessed region can be formed on a semiconductor substrate, and peripheral semiconductor devices can be formed on a recessed horizontal surface of the...
US-9,601,501 Nonvolatile memory cell structure with assistant gate and memory array thereof
An NVM array includes a plurality of NVM cells, a plurality of word lines extending along a first direction, a plurality of bit lines extending along a second...
US-9,601,500 Array of non-volatile memory cells with ROM cells
A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region...
US-9,601,499 One-time programmable memory cell capable of reducing leakage current and preventing slow bit response, and...
A one time programmable (OTP) memory cell includes a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor...
US-9,601,498 Two-terminal nanotube devices and systems and methods of making same
A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least...
US-9,601,497 Static random access memory and method of manufacturing the same
A Static Random Access Memory (SRAM) cell includes a first pull-up transistor and a first pull-down transistor, a second pull-up transistor and a second...
US-9,601,496 Semiconductor device having sacrificial layer pattern with concave sidewalls and method fabricating the same
In a method of fabricating a semiconductor device, sacrificial layer patterns are formed by leaving portions of sacrificial layers, instead of completely...
US-9,601,495 Three-dimensional semiconductor device with co-fabricated adjacent capacitor
A three-dimensional semiconductor device includes a semiconductor substrate, fin(s) coupled to the substrate and surrounded at a bottom portion thereof by...
US-9,601,494 Semiconductor devices having a supporter and methods of fabricating the same
Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices include an interlayer insulating layer on a semiconductor...
US-9,601,493 Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making
An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The...
US-9,601,492 FinFET devices and methods of forming the same
FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and an insulating wall. The...
US-9,601,491 Vertical field effect transistors having epitaxial fin channel with spacers below gate structure
A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings...
US-9,601,490 FinFET work function metal formation
An improved method and structure for fabrication of replacement metal gate (RMG) field effect transistors is disclosed. P-type field effect transistor (PFET)...
US-9,601,489 Dummy metal gate structures to reduce dishing during chemical-mechanical polishing
The described embodiments of mechanisms for placing dummy gate structures next to and/or near a number of wide gate structures reduce dishing effect for gate...
US-9,601,488 Gate-all-around semiconductor device and method of fabricating the same
The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating...
US-9,601,487 Power transistor
A power transistor includes a number of transistor cells. Each transistor cell includes a source region, a drain region, a body region and a gate electrode....
US-9,601,486 ESD snapback based clamp for finFET
There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a...
US-9,601,485 Reverse-conducting IGBT with buffer layer and separation layer for reducing snapback
In the reverse-conducting IGBT according to the present invention, an n-type buffer layer surrounds a p-type collector layer. A p-type separation layer...
US-9,601,484 Magnetic multilayer structure
A mechanism is provided for an integrated laminated magnetic device. A substrate and a multilayer stack structure form the device. The multilayer stack...
US-9,601,483 Semiconductor device
A semiconductor device according to an embodiment includes a normally-off transistor having a first drain, a first source electrically connected to a source...
US-9,601,482 Economical and environmentally friendly chemical mechanical polishing for III-V compound semiconductor device...
Compound semiconductor devices and methods for fabricating compound semiconductor devices (e.g., III-V devices) based on aspect ratio trapping are provided in...
US-9,601,481 Semiconductor device
A semiconductor device includes a first electrode, a first semiconductor layer of a first dopant type on the first electrode. A first region of the...
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