Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,601,480 Single junction bi-directional electrostatic discharge (ESD) protection circuit
In an embodiment, an ESD protection circuit may include a silicon-controlled rectifier (SCR) and a diode sharing a PN junction and forming a bi-directional ESD...
US-9,601,479 Protection circuit, circuit employing same, and associated method of operation
A buffer or voltage protection circuit, a circuit including same, and an associated method of operation are disclosed. In one example embodiment, the integrated...
US-9,601,478 Oxide definition (OD) gradient reduced semiconductor device
An integrated circuit (IC) semiconductor device has a high oxide definition (OD) density region, a low OD density region adjacent to the high OD density region,...
US-9,601,477 Integrated circuit having spare circuit cells
Aspects of the disclosure include an integrated circuit that includes a plurality of functional circuit cells and a plurality of inactive spare functional...
US-9,601,476 Optoelectronics and CMOS integration on GOI substrate
A method of forming an optoelectronic device and a silicon device on a single chip. The method may include; forming a stack of layers on a substrate in a first...
US-9,601,475 Workpiece with semiconductor chips, semiconductor device and method for producing a workpiece with...
A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main...
US-9,601,474 Electrically stackable semiconductor wafer and chip packages
A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating...
US-9,601,473 Power device cassette with auxiliary emitter contact
A press pack module includes a collector module terminal, an emitter module terminal, a gate module terminal, and an auxiliary module terminal. Each IGBT...
US-9,601,472 Package on package (POP) device comprising solder connections between integrated circuit device packages
Some features pertain to a package on package (PoP) device that includes a first package, a first solder interconnect coupled to the first integrated circuit...
US-9,601,471 Three layer stack structure
Vertically stacked system in package structures are described. In an embodiment, a package includes a first level molding and fan out structure, a third level...
US-9,601,470 Stacked semiconductor device, printed circuit board, and method for manufacturing stacked semiconductor device
A stacked semiconductor device includes a first semiconductor package and a second semiconductor package stacked thereon, and further includes a plate member...
US-9,601,469 Package-on-package modules, electronic systems including the same, and memory cards including the same
Package-on-package (PoP) modules are provided. The PoP module includes a lower package and an upper package disposed over the lower package. The lower package...
US-9,601,468 Magnetic contacts
Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication...
US-9,601,467 Microelectronic package with horizontal and vertical interconnections
In a microelectronic package, a first wire bond wire is coupled to an upper surface of a substrate. A first bond mass is coupled to another end of the first...
US-9,601,466 Semiconductor package and method of manufacturing the same
Provided is a semiconductor package and a method of making same, including a first package substrate; a first semiconductor chip mounted on the first package...
US-9,601,465 Chip-stacked semiconductor package and method of manufacturing the same
A chip-stacked semiconductor package includes a first chip having a first front surface, a first back surface, and a first connection member on the first front...
US-9,601,464 Thermally enhanced package-on-package structure
In some embodiments, a semiconductor device package may include a semiconductor device package on package assembly. The package on package assembly may include...
US-9,601,463 Fan-out stacked system in package (SIP) and the methods of making the same
An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a...
US-9,601,462 Semiconductor device and method of forming UBM structure on back surface of TSV semiconductor wafer
A semiconductor device has a plurality of conductive vias formed through the semiconductor die with a first insulating layer around the conductive vias. A...
US-9,601,461 Semiconductor device and method of forming inverted pyramid cavity semiconductor package
A semiconductor device has a first substrate. A conductive layer is formed over the first substrate. A first cavity is formed through the first substrate and...
US-9,601,460 Chip package including recess in side edge
A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate and adjoins a side edge of the semiconductor...
US-9,601,459 Method for aligning micro-electronic components
Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced...
US-9,601,458 Stacked semiconductor package including connections electrically connecting first and second semiconductor packages
A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first...
US-9,601,457 Method for making an electrical connection in a blind via and electrical connection obtained
Method comprising steps as follows: a) depositing a meltable ball on a first conducting zone located in a blind hole formed on a first face of a first...
US-9,601,456 System-in-package module and manufacture method for a system-in-package module
A system-in-package module includes a non-memory chip, a bundled memory, and an encapsulation package material. The non-memory chip has a plurality of pads. The...
US-9,601,455 Semiconductor device and method for making semiconductor device
A semiconductor device includes: a substrate including a base member having a main surface and a back surface facing opposite in a thickness direction; a...
US-9,601,454 Method of forming a component having wire bonds and a stiffening layer
Microelectronic components and methods forming such microelectronic components are disclosed herein. The microelectronic components may include a plurality of...
US-9,601,453 Semiconductor package
Provided is a semiconductor package. The semiconductor package includes: a first die that is a monolithic type die, a driver circuit and a low-side output power...
US-9,601,452 High-conductivity bonding of metal nanowire arrays
A thermally-conductive and mechanically-robust bonding method for attaching a metal nanowire (MNW) array to an adjacent surface includes the steps of: removing...
US-9,601,451 Apparatus and methods for creating environmentally protective coating for integrated circuit assemblies
Example methods, apparatus, and products for creating an environmentally protective coating for integrated circuit assemblies are described herein. A preform...
US-9,601,450 Semiconductor package
A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element...
US-9,601,449 Thin layer deposition apparatus utilizing a mask unit in the manufacture of a display device
A mask unit for depositing a thin layer in a display device. The mask unit includes: a bead mask support which includes a plate; and a bead mask which is placed...
US-9,601,448 Electrode connection structure and electrode connection method
An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically...
US-9,601,447 Semiconductor device including plural semiconductor chips stacked on substrate
A semiconductor chip at least includes a row of first electrode pad group, which includes at least one first independent electrode pad and multiple first common...
US-9,601,446 Method of fabricating a bond pad structure
A method of forming a bond pad structure is provided. The method includes forming a first conductive layer over a substrate and depositing a first dielectric...
US-9,601,445 Semiconductor packages
Semiconductor packages are provided. The semiconductor packages may include a base film having a top surface and a bottom surface, a circuit pattern disposed on...
US-9,601,444 Cable mounted modularized signal conditioning apparatus system
A modularized signal conditioning apparatus system includes at least two slots formed in a coaxial cable. The slots are spaced apart so as to not reduce the...
US-9,601,443 Test structure for seal ring quality monitor
A semiconductor structure includes a daisy chain adjacent to an edge of a semiconductor chip. The daisy chain includes a plurality of horizontal metal lines...
US-9,601,442 Half-mold type mold package
A mold package being a half-mold type includes: a substrate includes a first face and a second face; an electronic component that is mounted on the first face;...
US-9,601,441 Semiconductor device and method for manufacturing semiconductor device
An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for...
US-9,601,440 Method for manufacturing semiconductor device and exposure mask used in the same method
A method for manufacturing a semiconductor device is disclosed in which the probability of occurrence of a crack is reduced and in which manufacturing cost is...
US-9,601,439 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate, a die disposed over the substrate, and including a die pad disposed over the die and a seal ring disposed at a...
US-9,601,438 Semiconductor device and method for manufacturing the same
According to one embodiment, there is disclosed a semiconductor device which has a wiring substrate, a semiconductor element mounted on the wiring substrate, a...
US-9,601,437 Plasma etching and stealth dicing laser process
Consistent with an example embodiment, a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices...
US-9,601,436 Method for semiconductor wafer alignment
A semiconductor wafer is provided. The semiconductor wafer includes a base layer having an active region and an edge region. A number of semiconductor devices...
US-9,601,435 Semiconductor package with embedded components and method of making the same
A semiconductor package may include a lower substrate with one or more electronic components attached to a surface thereof and an upper substrate with one or...
US-9,601,434 Semiconductor device and method of forming openings through insulating layer over encapsulant for enhanced...
A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed....
US-9,601,433 Semiconductor device and method of manufacturing the same
In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become...
US-9,601,432 Advanced metallization for damage repair
An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the...
US-9,601,431 Dielectric/metal barrier integration to prevent copper diffusion
An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.