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Patent # Description
US-9,601,430 Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes...
US-9,601,429 Semiconductor device, electronic component, and electronic device including memory cell comprising first...
A highly reliable semiconductor device. In a configuration where a precharged source line is discharged to a bit line by establishing electrical continuity...
US-9,601,428 Semiconductor fuses with nanowire fuse links and fabrication methods thereof
Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse,...
US-9,601,427 Semiconductor device including plural types of resistors and manufacturing method of the semiconductor device
A semiconductor device (1) includes a first metal wiring layer (11) formed on a substrate (10), an interlayer insulating film (12) formed on the first metal...
US-9,601,426 Interconnect structure having subtractive etch feature and damascene feature
Methods of forming an interconnect structure include depositing a first conductive material on a substrate. Aspects include subtractively etching the conductive...
US-9,601,425 Circuit substrate and semiconductor package structure
The invention provides a circuit substrate and a semiconductor package structure. The circuit substrate includes a core substrate having a chip-side surface and...
US-9,601,424 Interposer and methods of forming and testing an interposer
A method of forming and testing an interposer includes forming vias in a semiconductor material of a wafer having a front side and a back side. The method...
US-9,601,423 Under die surface mounted electrical elements
A laminate includes a buildup layer having a top and a bottom and a solder mask contacting the top. The laminate also includes a circuit element disposed on the...
US-9,601,422 Printed wiring board, semiconductor package, and method for manufacturing printed wiring board
A printed wiring board includes a first interlayer, a first conductive layer on first-surface side of the first interlayer, a second conductive layer on...
US-9,601,421 BBUL material integration in-plane with embedded die for warpage control
An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a...
US-9,601,420 Semiconductor device and method of manufacturing the same
A semiconductor device includes a stack structure of a conductive line and an insulating capping line extending in a first direction on a substrate, a plurality...
US-9,601,419 Stacked leadframe packages
A multi-package unit having stacked packages is provided. A multi-package unit may include a first package and a second package mounted on the first package....
US-9,601,418 Stacked half-bridge package
According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input,...
US-9,601,417 "L" shaped lead integrated circuit package
Various aspects provide for bending a bending a lead frame of a semiconductor device package into a shape of an "L" and mounting the package on a substrate. A...
US-9,601,416 Lead frame, mold and method of manufacturing lead frame with mounted component
A lead frame includes one metal plate 10 having a terminal 15, and the other metal plate 50 joined to the one metal plate 10, on which a mounted component 91 is...
US-9,601,415 Method of manufacturing semiconductor device and semiconductor device
In a method of manufacturing a semiconductor device according to an embodiment, a lead frame is provided, the lead frame having a trench part formed thereon so...
US-9,601,414 Method for preventing die pad delamination
The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a...
US-9,601,413 Cavity package with die attach pad
A cavity package is provided. The package can include a metal leadframe and a substrate attached to an interposer formed as part of the leadframe. The substrate...
US-9,601,412 Three-dimensional package structure
The present invention discloses a three-dimensional package structure. The first conductive element comprises a top surface, a bottom surface and a lateral...
US-9,601,411 Semiconductor structure
A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a wafer substrate having a top surface and a...
US-9,601,410 Semiconductor device and method
A semiconductor device and method are provided which utilizes a single mask to form openings for both a through substrate via as well as for a through...
US-9,601,409 Protruding contact for integrated chip
The present disclosure relates to a method of forming a back-end-of-the-line metal contact that eliminates RC opens caused by metal dishing during chemical...
US-9,601,408 Semiconductor device
A semiconductor device of the present invention includes a semiconductor element having an upper surface and a lower surface, a metal plate thermally connected...
US-9,601,407 System-in-package module and method for forming the same
A system-in-package (SiP) module is disclosed. The SiP module includes a substrate and a dam on the substrate. The dam defines a cavity. At least one chip is on...
US-9,601,406 Copper nanorod-based thermal interface material (TIM)
A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally...
US-9,601,405 Semiconductor package with an enhanced thermal pad
A semiconductor package having a substrate, a thermal pad, and a semiconductor die is disclosed. The thermal pad may have a heat conductive body extending...
US-9,601,404 Thermal resistance measuring method and thermal resistance measuring device
A temperature of a semiconductor element is measured based on a temperature coefficient of a voltage between the first electrode and the second electrode when...
US-9,601,403 Electronic package and fabrication method thereof
An electronic package is provided, which includes: a first circuit structure; at least first electronic element disposed on a surface of the first circuit...
US-9,601,402 Package apparatus and manufacturing method thereof
A package apparatus comprises a first wiring layer, a metal layer, a conductive pillar layer, a passive component, a first molding compound layer, a second...
US-9,601,401 Solventless one liquid type cyanate ester-epoxy composite resin composition
The present invention is a solventless one liquid type cyanate ester-epoxy resin composition having high thermal resistance as well as excellent storage...
US-9,601,400 Glass/ceramic replacement of epoxy for high temperature hermetically sealed non-axial electronic packages
A high temperature, non-cavity package for non-axial electronics is designed using a glass ceramic compound with that is capable of being assembled and...
US-9,601,399 Module arrangement for power semiconductor devices
A module arrangement for power semiconductor devices, including one or more power semiconductor modules, wherein the one or more power semiconductor modules...
US-9,601,398 Thin wafer handling and known good die test method
A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element...
US-9,601,397 Microwave probe, plasma monitoring system including the microwave probe, and method for fabricating...
Disclosed herein are a microwave probe capable of precisely detecting a plasma state in a plasma process, a plasma monitoring system including the probe, and a...
US-9,601,396 3D NAND staircase CD control by using interferometric endpoint detection
Embodiments of the present disclosure provide methods for forming stair-like structures in manufacturing three dimensional (3D) stacking of semiconductor chips....
US-9,601,395 Methods for post-epitaxial warp prediction and control
In one aspect, a method of predicting warp in a plurality of wafers after an epitaxial layer deposition process is provided. The method includes receiving, by a...
US-9,601,394 Substrate processing apparatus, substrate processing method and memory medium
A substrate processing system includes a film-forming device to form photosensitive film on substrate, an exposure device to expose the film on the substrate, a...
US-9,601,393 Selecting one or more parameters for inspection of a wafer
Computer-implemented methods, computer-readable media, and systems for selecting one or more parameters for inspection of a wafer are provided.
US-9,601,392 Device characterization by time dependent charging dynamics
A method and device for characterizing a DC parameter of a SRAM device based on TDCD are provided. Embodiments include forming a SRAM test device, the SRAM test...
US-9,601,391 Mechanical stress measurement during thin-film fabrication
A method and system are provided for determining mechanical stress experienced by a film during fabrication thereof on a substrate positioned in a vacuum...
US-9,601,390 Silicon germanium fin formation via condensation
A method of forming a finFET device comprises forming a fin in a silicon layer of a substrate, forming a hardmask layer on a top surface of the fin, forming an...
US-9,601,389 Method for local thinning of top silicon layer of SOI wafer
A method for local thinning of a top silicon layer of a SOI wafer includes the consecutive steps of: providing a SOI wafer which successively includes a bottom...
US-9,601,388 Integrated high-K/metal gate in CMOS process flow
A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a first...
US-9,601,387 Method of making threshold voltage tuning using self-aligned contact cap
Methods of forming a PFET dielectric cap with varying concentrations of H.sub.2 reactive gas and the resulting devices are disclosed. Embodiments include...
US-9,601,386 Fin isolation on a bulk wafer
A method for forming a semiconductor device includes etching first fins into a bulk semiconductor substrate and exposing a portion of the first fins through a...
US-9,601,385 Method of making a dual strained channel semiconductor device
A method of forming a semiconductor device includes forming on a substrate mandrels made from a semiconductor material. A semiconductor material having a...
US-9,601,384 Method of forming a semiconductor device comprising first and second nitride layers
A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well...
US-9,601,383 FinFET fabrication by forming isolation trenches prior to fin formation
A semiconductor structure for a FinFET in fabrication is provided, the structure including a bulk semiconductor substrate initially with a hard mask over the...
US-9,601,382 Method for the formation of a FinFET device with epitaxially grown source-drain regions having a reduced...
Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer (of either SOI or bulk type). Elongated gates...
US-9,601,381 Method for the formation of a finFET device with epitaxially grown source-drain regions having a reduced...
Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer. Elongated gates of a second semiconductor...
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