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Patent # Description
US-9,601,380 Fin end spacer for preventing merger of raised active regions
After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a...
US-9,601,379 Methods of forming metal source/drain contact structures for semiconductor devices with gate all around channel...
In one example, the method disclosed herein includes, among other things, forming a sacrificial structure around a plurality of stacked substantially un-doped...
US-9,601,378 Semiconductor fins for FinFET devices and sidewall image transfer (SIT) processes for manufacturing the same
A method of forming a semiconductor structure includes providing a semiconductor substrate, forming at least one precursor semiconductor fin from the...
US-9,601,377 FinFET formation process and structure
A FinFET and methods for forming a FinFET are disclosed. In a method, first trenches are formed in a substrate. First isolation regions are then formed in the...
US-9,601,376 Semiconductor device and method of manufacturing a semiconductor device having a glass piece and a...
A semiconductor device includes a glass piece and an active semiconductor element formed in a single-crystalline semiconductor portion. The single-crystalline...
US-9,601,375 UV-cure pre-treatment of carrier film for wafer dicing using hybrid laser scribing and plasma etch approach
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor...
US-9,601,374 Semiconductor die assembly
A semiconductor die assembly having a solderball wirebonded to a substrate. As an example, the semiconductor die assembly may include the solderball attached to...
US-9,601,373 Semiconductor device and method for manufacturing the same
A method for manufacturing a semiconductor device is provided. The method includes the following operations: (i) forming a transistor having a source, a drain...
US-9,601,372 Method of forming metal pads with openings in integrated circuits including forming a polymer plug extending...
A device includes a metal pad, and a passivation layer including portions overlapping edge portions of the metal pad. A Post-Passivation-Interconnect (PPI)...
US-9,601,371 Interconnect structure with barrier layer
Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect...
US-9,601,370 Nonvolatile semiconductor memory device and method of manufacturing the same
The memory cell array includes a memory string and a select transistor. The memory string includes plural memory cells connected in series, the memory string...
US-9,601,369 Semiconductor device and method of forming conductive vias with trench in saw street
A semiconductor wafer has a plurality of semiconductor die separated by a peripheral region. A trench is formed in the peripheral region of the wafer. A via is...
US-9,601,368 Semiconductor device comprising an oxygen diffusion barrier and manufacturing method
An embodiment of a method of manufacturing a semiconductor device includes forming an oxygen diffusion barrier on a first surface of a Czochralski or magnetic...
US-9,601,367 Interconnect level structures for confining stitch-induced via structures
A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A...
US-9,601,366 Trench formation for dielectric filled cut region
A method for forming a gate cut region includes forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a...
US-9,601,365 Peeling device, peeling system, and peeling method
A peeling device separates a superposed substrate, in which a target substrate and a support substrate are joined to each other with an adhesive, into the...
US-9,601,364 Low temperature adhesive resins for wafer bonding
A method for adhesive bonding in microelectronic device processing is provided that includes bonding a handling wafer to a front side of a device wafer with an...
US-9,601,363 Thin substrate electrostatic chuck system and method
In various aspects of the disclosure, a semiconductor substrate processing system may include an electrostatic chuck for holding a semiconductor substrate...
US-9,601,362 High speed substrate aligner apparatus
A substrate aligner providing minimal substrate transporter extend and retract motions to quickly align substrate without back side damage while increasing the...
US-9,601,361 Fixture for conveying a mask plate for the production of thin film transistor liquid crystal display
A fixture for conveying a mask plate comprising: a conveying bracket; and a fixation structure that is arranged on the conveying bracket and configured to fix...
US-9,601,360 Wafer transport method
A wafer transport method is provided. The wafer transport method includes loading an initial carrier containing a first wafer and a second wafer on a first...
US-9,601,359 Substrate holding device, semiconductor fabrication device, and substrate clamping ascertainment method
A substrate holding device is provided with an electrostatic chuck that has an electrode therein and is provided with a substrate holding surface, on one side...
US-9,601,358 Substrate treatment apparatus, and substrate treatment method
The inventive substrate treatment apparatus includes: a rotative treatment control unit which controls a first chemical liquid supplying unit and a second...
US-9,601,357 Substrate processing device and substrate processing method
A substrate processing apparatus and method includes, a plate that has a size equal to or larger than a principal face of the substrate, and has a horizontal...
US-9,601,356 Systems and methods for controlling release of transferable semiconductor structures
The disclosed technology relates generally to methods and systems for controlling the release of micro devices. Prior to transferring micro devices to a...
US-9,601,355 Via structure for packaging and a method of forming
A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying...
US-9,601,354 Semiconductor manufacturing for forming bond pads and seal rings
An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor...
US-9,601,353 Packages with molding structures and methods of forming the same
A method includes molding a device die in a molding material, wherein a metal pillar of the device die is exposed through a surface of the molding material. A...
US-9,601,352 Method of localized annealing of semi-conducting elements using a reflective area
A method of making crystal semi-conducting material-based elements, including providing a support having amorphous semi-conducting material-based...
US-9,601,351 Method of manufacturing a semiconductor device
The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first...
US-9,601,350 Bonding-substrate fabrication method, bonding substrate, substrate bonding method, bonding-substrate...
[Problem] To provide a substrate bonding technique having a wide range of application. [Solution] A silicon thin film is formed on a bonding surface, and the...
US-9,601,349 Etching method
The invention is directed to a method for patterning a material layer. The method comprises steps of providing a material layer having a first hard mask layer...
US-9,601,348 Interconnect structure and method of forming same
A method of forming a semiconductor device is provided. Metallic interconnects are formed in a dielectric layer of the semiconductor device. A hard mask is used...
US-9,601,347 Forming semiconductor fins with self-aligned patterning
A method for fabricating a semiconductor device comprises removing a portion of a substrate to form a first cavity in the substrate and depositing an insulator...
US-9,601,346 Spacer-damage-free etching
A method of patterning a semiconductor device is disclosed. A tri-layer photoresist is formed over a plurality of patterned features. The tri-layer photoresist...
US-9,601,345 Fin trimming in a double sit process
A semiconductor structure and the method of forming that semiconductor structure. The method includes formation of a plurality of fins from a layer of...
US-9,601,344 Method of forming pattern for semiconductor device
The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor...
US-9,601,343 Semiconductor device manufacturing method
In a semiconductor device manufacturing method, on a film to be processed, a mask material film is formed which has pattern openings for a plurality of contact...
US-9,601,342 FinFETs with strained well regions
A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having...
US-9,601,341 Method of etching
A method of etching a feature in a substrate includes forming a mask structure over the substrate, the mask structure defining at least one re-entrant opening,...
US-9,601,340 Electronic device having quantum dots and method of manufacturing the same
Provided are electronic devices having quantum dots and methods of manufacturing the same. An electronic device includes a first nanorod, a quantum dot disposed...
US-9,601,339 Methods for depositing fluorine/carbon-free conformal tungsten
Provided are atomic layer deposition methods to deposit a tungsten film or tungsten-containing film using a tungsten-containing reactive gas comprising one or...
US-9,601,338 Thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof, and...
A thin film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device are provided. The array...
US-9,601,337 Manufacturing method of graphene modulated high-K oxide and metal gate MOS device
A manufacturing method of a graphene modulated high-k oxide and metal gate Ge-based MOS device, which comprises the following steps: 1) introducing a graphene...
US-9,601,336 Trench field-effect device and method of fabricating same
The present invention provides a method of fabricating a trench field-effect device. The method includes: providing a substrate including an epitaxial layer...
US-9,601,335 Trench formation for dielectric filled cut region
A method for forming a gate cut region includes forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a...
US-9,601,334 Semiconductor device and the method of manufacturing the same
A semiconductor device according to the invention includes p-type well region 3 and n.sup.+ source region 4, both formed selectively in the surface portion of...
US-9,601,333 Etching process
A method includes providing a semiconductor substrate; forming a doping oxide layer on the semiconductor substrate; forming a patterning layer on the doping...
US-9,601,332 Systems and method for ohmic contacts in silicon carbide devices
A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film...
US-9,601,331 Pattern forming method and manufacturing method of semiconductor device
A pattern forming method includes forming a spin on dielectric film on a substrate, washing the spin on dielectric film by using a washing liquid, drying a...
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