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Patent # Description
US-9,608,687 Computer based activity center
The present invention relates to a casing for accommodating a computer based device or an activity board having an input/output port interface and/or an...
US-9,608,686 Case for cooling an electronic device via an endothermic reaction
A case for cooling a portable electronic device, the case including a housing and a cartridge. The housing holds the electronic device and has a cartridge...
US-9,608,685 Deformable seal for an electronic device
An electronic device that includes a deformable feature designed to seal two or more parts of the electronic device is disclosed. The deformable feature may be...
US-9,608,684 Network-on-chip based computing devices and systems
Several embodiments of the present technology are related to network-on-chip based integrated circuits, methods of manufacturing or fabricating such integrated...
US-9,608,683 Millimeter wave transmission device, millimeter wave transmission method, and millimeter wave transmission system
The device includes: a signal generating unit generating a millimeter wave signal by signal processing of an input signal; a coupling circuit transmitting an...
US-9,608,682 Interference reduction for multiple signals
The present invention reduces the degradation in performance of one or more radio signals that are co-transmitted with a first radio signal from the same...
US-9,608,681 Output driver architecture with low spur noise
In one embodiment, an integrated circuit includes: a first input pad to receive a radio frequency (RF) signal; a radio receiver to process the RF signal and...
US-9,608,680 Messaging devices and methods
An electronic messaging device includes a receiver configured to receive a message at one of a first operational frequency and second operational frequency. The...
US-9,608,679 Very low intermediate frequency (VLIF) receiver and a method of controlling a VLIF receiver
A very low intermediate frequency (VLIF) receiver and a method of controlling a VLIF receiver. The method comprises estimating energy levels in first and second...
US-9,608,678 Method and apparatus for mitigating interference between wireless local area network (WLAN) communications and...
A wireless device including a first receiver and a second receiver. The first receiver is configured to receive a first signal transmitted on a first network...
US-9,608,677 Systems and methods of RF power transmission, modulation, and amplification
An apparatus, system, and method are provided for energy conversion. For example, the apparatus can include a trans-impedance node, a reactive element, and a...
US-9,608,676 Digital pre-distortion systems in transmitters
Various digital pre-distortion systems for use in transmitters are disclosed. The digital pre-distortion system comprises an observing path, which performs...
US-9,608,675 Power tracker for multiple transmit signals sent simultaneously
Techniques for generating a power tracking supply voltage for a circuit (e.g., a power amplifier) are disclosed. The circuit may process multiple transmit...
US-9,608,674 Method and system for 60 GHz distributed communication
Methods and systems for 60 GHz distributed communication are disclosed and may include generating IF signals from baseband signals in a computing device with...
US-9,608,673 Transmitter and method of processing transmission signals
A transmitter and method are provided for processing a transmission signal. The transmitter includes an FEM that switches a plurality of band signals for a...
US-9,608,672 Apparatus and method for generating base band receive signals
An apparatus for generating base band receive signals includes a first analog-to-digital converter module generating a first digital high frequency receive...
US-9,608,671 Error detection method of variable-length coding code stream and decoding and error detection apparatus
An error detection method of a variable-length coding (VLC) code stream includes at least the following steps: decoding a data frame of the VLC code stream; and...
US-9,608,670 Reliable data reading with data set screening by error injection
According to one embodiment, a method for processing data includes determining whether a PES is invalid while reading data from a magnetic medium using at least...
US-9,608,669 Latency reduced error correction scheme with error indication function for burst error correction codes
The present discloses provides a decoding method, decoding apparatus and decoder for correcting burst errors. In particular, the decoding method for correcting...
US-9,608,668 Error correcting apparatus, error correcting method, and program
Provided is an error correcting method including: executing, by an error-position detector, a determination process if a received word fails to satisfy a...
US-9,608,667 Method and apparatus for decoding non-binary parity check code
A method of decoding a non-binary Low Density Parity Check (LDPC) code is provided. The method includes a plurality of messages to perform hard decision for all...
US-9,608,666 Non-concatenated FEC codes for ultra-high speed optical transport networks
A decoder performs forward error correction based on quasi-cyclic regular column-partition low density parity check codes. A method for designing the parity...
US-9,608,665 Adaptive compression of data
A method of encoding data includes determining a magnitude of change between a first value associated with first data and a second value associated with second...
US-9,608,664 Compression of integer data using a common divisor
According to one embodiment of the present invention, a system for compressing data determines a common divisor for a set of values comprising integers. The...
US-9,608,662 Apparatus and method for converting floating-point operand into a value having a different format
A data processing apparatus has floating-point add circuitry to perform a floating-point addition operation for adding or subtracting two floating-point values....
US-9,608,661 Software programmable cellular radio architecture for wide bandwidth radio systems including telematics and...
A cellular radio architecture that includes a programmable bandpass sampling radio frequency front-end and an optimized digital baseband. The architecture...
US-9,608,660 Digital-to-analog converter with switching elements controlled by a microcontroller
A digital-to-analog converter (DAC) is described. The DAC comprises a resistor having a resistance R and a capacitor having a capacitance C. The DAC comprises a...
US-9,608,659 Analog/digital conversion circuit
An A/D conversion circuit includes: first/second pulse circulation circuits delaying an input signal and circulating a pulse signal; a circulation number...
US-9,608,658 Segmented successive approximation register (SAR) analog-to-digital converter (ADC) with reduced conversion time
Certain aspects of the present disclosure provide a segmented successive approximation register (SAR) analog-to-digital converter (ADC). One example ADC...
US-9,608,657 A/D converter circuit, pipeline A/D converter, and wireless communication device
An A/D converter circuit has an amplifier circuit to amplify an input signal and output a first amplification signal and a second amplification signal, the...
US-9,608,656 Symmetrical capacitor arrays succesive approximation register (SAR) analog-to-digital converter (ADC)
Analog-to-digital converter (ADC) circuitry includes a first binary-weighted capacitor array having a total capacitance of 2.sup.n-2C. The value of n represents...
US-9,608,655 ADC background calibration with dual conversions
An analog-to-digital converter (ADC) system can sample an input voltage for at least a first conversion into a first N.sub.1-bit digital value and to use the...
US-9,608,654 Semiconductor device including an analog/digital conversion circuit
The present invention provides a semiconductor device having a high-speed A/D conversion circuit realizing improvement in noise resistance. A semiconductor...
US-9,608,653 Method and device for compensating bandwidth mismatches of time interleaved analog to digital converters
A device can be used for compensating bandwidth mismatches of time interleaved analog to digital converters. A processor of the device determines, for each...
US-9,608,652 Methods and apparatus for reducing timing-skew errors in time-interleaved analog-to-digital converters
A time-interleaved (TI) analog-to-digital converter (ADC) architecture employs a low resolution coarse ADC channel that samples an input analog signal at a...
US-9,608,651 Systems and methods of phase-locked loop involving closed-loop, continuous frequency range, auto calibration...
Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage...
US-9,608,650 Method and device for controlling single-phase phase-locked loop
The present disclosure provides a single-phase PLL controlling method and a single-phase PLL controlling device. The device includes a first FIR filter, a...
US-9,608,649 Analog phase-locked loop with enhanced acquisition
An analog phase-locked loop (PLL) is disclosed, comprising a voltage controlled oscillator (VCO); a frequency divider having its input connected to an output of...
US-9,608,648 Wideband direct modulation with two-point injection in digital phase locked loops
A digitally controlled oscillator (DCO) modulation apparatus and method provides a wideband phase-modulated signal output. An exemplary modulator circuit uses...
US-9,608,647 System and method for voltage-controlled oscillator calibration
A system and method for calibrating a Voltage-Controlled Oscillator (VCO) having both fine-tuning control and coarse-tuning control. The VCO frequency can vary...
US-9,608,646 PLL circuit and operation method
A PLL circuit having a desired performance is provided. A PLL circuit (100) includes a phase comparator (11) that detects a phase difference; a voltage control...
US-9,608,645 Phase-lock loop
In one implementation an output signal of an oscillator is varied to be within a desired frequency band with respect to a reference signal, the output signal...
US-9,608,644 Phase-locked loop having sub-sampling phase detector
An example phase-locked loop (PLL) circuit includes a voltage controlled oscillator (VCO) configured to generate an output clock based on an oscillator control...
US-9,608,643 Delay lock loop
A delay lock loop is provided. A delay unit delays a first clock signal to generate a second clock signal according to the delay factor. An elimination unit...
US-9,608,642 Delay lock loop
A delay lock loop including a selection unit, a delay unit, and a phase detection unit is provided. The selection unit receives a non-inverted clock signal and...
US-9,608,641 All digital phase locked loop
An all-digital phase-locked loop (AD-PLL) and related methods and computer readable medium are provided. The AD-PLL comprises a reference phase generator for...
US-9,608,640 Receiving circuit and method for controlling frequency
A receiving circuit includes: a detector configured to detect a position at which logics of first data and second data acquired by sampling received data using...
US-9,608,639 Semiconductor device
A semiconductor device may include a delay line including a first group of unit delay cells and a second group of unit delay cells. The first group of unit...
US-9,608,637 Dynamic voltage level shifters employing pulse generation circuits, and related systems and methods
Dynamic voltage level shifters employing pulse generation circuits are disclosed. In one aspect, a dynamic voltage level shifter includes a dynamic voltage...
US-9,608,636 High-voltage tolerant input voltage buffer circuit
Described is an apparatus comprising a first node to receive signal; a second node to provide an output signal; a voltage limiter circuit operating under a...
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