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Patent # Description
US-9,608,130 Semiconductor device having trench capacitor structure integrated therein
Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate. The...
US-9,608,129 Semiconductor device and Zener diode having branch impurity regions
A semiconductor device includes a substrate, a well region of a first-conductivity type disposed in the substrate, a first impurity region of a...
US-9,608,128 Body of doped semiconductor material having scattering centers of non-doping atoms of foreign matter disposed...
A method for producing a body (1) consisting of doped semiconductor material having a defined mean free path length (lambda n) for free charge carriers (CP),...
US-9,608,127 Amorphous oxide thin film transistor, method for manufacturing the same, and display panel
Embodiments of the disclosed technology provide an amorphous oxide thin film transistor (TFT), a method for preparing an amorphous oxide TFT, and a display...
US-9,608,126 Semiconductor device and method of fabricating the same
A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, an interconnect structure, and an oxide...
US-9,608,125 Display substrate, its testing method and its manufacturing method
The present disclosure provides a display substrate, its testing method and its manufacturing method. A first testing terminal is connected to a gate electrode...
US-9,608,124 Semiconductor device
Provided is a transistor which has favorable transistor characteristics and includes an oxide semiconductor, and a highly reliable semiconductor device which...
US-9,608,123 Method for manufacturing semiconductor device
In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of...
US-9,608,122 Semiconductor device and method for manufacturing the same
A highly reliable semiconductor device with stable electrical characteristics and a method for manufacturing the semiconductor device are provided. A separation...
US-9,608,121 Method for manufacturing semiconductor device
To reduce defects in an oxide semiconductor film in a semiconductor device. To improve electrical characteristics of and reliability in the semiconductor device...
US-9,608,120 Image pickup unit and image pickup display system
A semiconductor device including a substrate, at least one gate electrode, at least two silicon oxide layers comprising a first silicon oxide layer and a second...
US-9,608,119 Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices...
Methods for fabricating semiconductor-metal-on-insulator (SMOI) structures include forming an acceptor wafer including an insulator material on a first...
US-9,608,118 Array substrate, display device and manufacturing method of array substrate
An array substrate, a display device and a method of producing the array substrate are provided, and the array substrate includes a substrate and a thin film...
US-9,608,117 Semiconductor devices including a finFET
A semiconductor device includes an active fin structure extending in a first direction, the active fin structure including protruding portions divided by a...
US-9,608,116 FINFETs with wrap-around silicide and method forming the same
A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a...
US-9,608,115 FinFET having buffer layer between channel and substrate
FinFET and fabrication method thereof. The FinFET fabrication method includes providing a semiconductor substrate; forming a plurality of trenches in the...
US-9,608,114 Semiconductor device including field effect transistors
A semiconductor device includes a buffer layer on a substrate, the buffer layer having a lattice constant different from that of the substrate, a fin structure...
US-9,608,113 Semiconductor device structure
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor...
US-9,608,112 BULEX contacts in advanced FDSOI techniques
The present disclosure provides, in accordance with some illustrative embodiments, a method of forming a semiconductor device, the method including providing an...
US-9,608,111 Recessed transistors containing ferroelectric material
Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an...
US-9,608,110 Methods of forming a semiconductor circuit element and semiconductor circuit element
The present disclosure provides methods of forming a semiconductor circuit element and a semiconductor circuit element, wherein the semiconductor circuit...
US-9,608,109 N-channel demos device
An n-channel DEMOS device a pwell finger defining a length and a width direction formed within a doped surface layer. A first nwell is on one side of the pwell...
US-9,608,108 Semiconductor device and method for manufacturing the same
A semiconductor substrate has a main surface with an n type offset region having a trench portion formed of a plurality of trenches extending in a direction...
US-9,608,107 Method and apparatus for MOS device with doped region
A semiconductor device is provided. The device may include a semiconductor layer; and a doped well disposed in the semiconductor layer and having a first...
US-9,608,106 Semiconductor device and method for forming the same
A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a...
US-9,608,105 Semiconductor structure with a doped region between two deep trench isolation structures
The density of a transistor array is increased by forming one or more deep trench isolation structures in a semiconductor material. The deep trench isolation...
US-9,608,104 Silicon carbide semiconductor device and method for manufacturing same
A silicon carbide semiconductor device includes: a vertical MOSFET having: a semiconductor substrate including a high-concentration impurity layer and a drift...
US-9,608,103 High electron mobility transistor with periodically carbon doped gallium nitride
A method for forming a high electron mobility transistor (HEMT) device with a plurality of alternating layers of one or more undoped gallium nitride (GaN)...
US-9,608,102 Gallium nitride material devices and associated methods
Gallium nitride material devices and methods associated with the same. In some embodiments, the devices may be transistors which include a conductive structure...
US-9,608,101 Semiconductor device
The present invention concerns semiconductor devices comprising a source electrode, a drain electrode and a semiconducting layer consisting of a single or...
US-9,608,100 High electron mobility transistor and method of manufacturing the same
According to example embodiments, a high electron mobility transistor (HEMT) includes: stack including a buffer layer, a channel layer containing a two...
US-9,608,099 Nanowire semiconductor device
A method for forming a nanowire device comprises forming a fin on a substrate, depositing a first layer of insulator material on the substrate, etching to...
US-9,608,098 Tunable FIN-SCR for robust ESD protection
One embodiment of the present invention relates to a silicon-controlled-rectifier (SCR). The SCR includes a longitudinal silicon fin extending between an anode...
US-9,608,097 Insulated gate bipolar transistor amplifier circuit
The present invention provides a lateral IGBT transistor comprising a bipolar transistor and an IGFET. The lateral IGBT comprises a low resistive connection...
US-9,608,096 Implementing stress in a bipolar junction transistor
Device structure and fabrication methods for a bipolar junction transistor. One or more trench isolation regions are formed in a substrate to define a device...
US-9,608,095 Thermoelectric conversion element and manufacturing method for the same
Concerning a thermoelectric conversion element, it is desired to provide a new spin current to charge current conversion material. A thermoelectric conversion...
US-9,608,094 Heterosection tunnel field-effect transistor (TFET)
A Tunnel Field-Effect Transistor (TFET) device is provided comprising at least one heterosection between the source region and the channel region. The at least...
US-9,608,092 Method of manufacturing a semiconductor device having a rectifying junction at the side wall of a trench
A method for forming a field-effect semiconductor device includes: providing a wafer having a main surface and a first semiconductor layer of a first...
US-9,608,091 Method for manufacturing a semiconductor device
The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are...
US-9,608,090 Method for fabricating semiconductor device having fin structure that includes dummy fins
A method for fabricating semiconductor device is disclosed. First, a substrate, and a sacrificial mandrel is formed on the substrate, in which the sacrificial...
US-9,608,089 Method of manufacturing thin-film transistor substrate
Provided is a method of manufacturing a thin-film transistor substrate, the method includes forming a semiconductor pattern layer on a substrate. A first...
US-9,608,088 Hybrid active-field gap extended drain MOS transistor
An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended...
US-9,608,087 Integrated circuits with spacer chamfering and methods of spacer chamfering
Semiconductor devices and methods for forming the devices with spacer chamfering. One method includes, for instance: obtaining a wafer with at least one source,...
US-9,608,086 Metal gate structure and method of formation
Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut...
US-9,608,085 Predisposed high electron mobility transistor
A predisposed high electron mobility transistor (HEMT) is disclosed. The predisposed HEMT includes a buffer layer, a HEMT channel layer on the buffer layer, a...
US-9,608,084 Emitter contact epitaxial structure and ohmic contact formation for heterojunction bipolar transistor
Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device includes a diffusion...
US-9,608,083 Semiconductor device
A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a...
US-9,608,082 Electro-mechanical switching devices
A switching device includes an opening disposed in a substrate. A source is disposed adjacent the opening and has a contact surface parallel to sidewalls of the...
US-9,608,081 Simple and cost-free MTP structure
Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes a substrate,...
US-9,608,080 Method and structure to reduce parasitic capacitance in raised source/drain silicon-on-insulator devices
An aspect of the invention is directed to a silicon-on-insulator device including a silicon layer on an insulating layer on a substrate; a raised source and a...
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