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Patent # Description
US-9,608,079 Semiconductor device having reduced drain-to-source capacitance
A semiconductor device includes a source finger electrode coupled to a source region in a semiconductor die, a drain finger electrode coupled to a drain region...
US-9,608,078 Semiconductor device with improved field plate
A transistor device includes a semiconductor body, a spacer layer, and a field plate. The spacer layer is over at least a portion of a surface of the...
US-9,608,077 Semiconductor structure and method for manufacturing the same
A method for manufacturing a semiconductor structure includes preparing a semiconductor substrate which includes a memory cell region and a peripheral circuit...
US-9,608,075 III-nitride semiconductor device with doped epi structures
A compound semiconductor device includes a first III-nitride buffer layer doped with carbon and/or iron, a second III-nitride buffer layer above the first...
US-9,608,074 Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device
A silicon carbide semiconductor device includes a silicon carbide substrate, a gate electrode, and a drain electrode. A trench is formed in a second main...
US-9,608,073 Semiconductor device and method of manufacturing semiconductor device
Provided is a semiconductor device comprising: a first conductivity type base layer having a MOS gate structure formed on its front surface side; a second...
US-9,608,072 Semiconductor device
A semiconductor device is provided with a first well region of a first conduction type having a first voltage (voltage VB) applied thereto, a second well region...
US-9,608,071 IGBT and IGBT manufacturing method
An IGBT manufacturing method is provided. The IGBT has an n-type emitter region, a p-type top body region, an n-type intermediate region, a p-type bottom body...
US-9,608,070 Semiconductor device comprising a field effect transistor and method of manufacturing the semiconductor device
A semiconductor device comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a...
US-9,608,069 Self aligned epitaxial based punch through control
A method of forming a semiconductor device that may include etching source and drain portions of a fin structure of a first semiconductor material selectively...
US-9,608,068 Substrate with strained and relaxed silicon regions
A method is provided for forming an integrated circuit. A trench is formed in a substrate. Subsequently, a silicon-germanium feature is formed in the trench,...
US-9,608,067 Hybrid aspect ratio trapping
A semiconductor structure includes a material stack located on a surface of a semiconductor substrate. The material stack includes, from bottom to top, a...
US-9,608,066 High-K spacer for extension-free CMOS devices with high mobility channel materials
A field effect transistor device includes a gate structure formed over a channel region in a semiconductor material. An inner spacer is formed on sidewalls of...
US-9,608,065 Air gap spacer for metal gates
A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and...
US-9,608,064 MOSFET structure and method for manufacturing same
Provided is a MOSFET, comprising: a substrate (100); a gate stack (500) on the substrate (100); source/drain regions (305) in the substrate on both sides of the...
US-9,608,063 Nanowire transistor structures with merged source/drain regions using auxiliary pillars
A nanowire transistor structure is fabricated by using auxiliary epitaxial nucleation source/drain fin structures. The fin structures include semiconductor...
US-9,608,062 Semiconductor structure and method of forming the same
The present invention provides a semiconductor structure including a fin structure formed on a substrate, and an isolation structure formed in the fin...
US-9,608,061 Fin field-effct transistors
A method for fabricating fin field-effect transistors includes providing a semiconductor substrate; and forming a plurality of fins on a surface of the...
US-9,608,060 Isolation structure for semiconductor device
A semiconductor structure includes a substrate, a semiconductor device in the substrate, and an isolating structure in the substrate and adjacent to the...
US-9,608,059 Semiconductor device with isolated body portion
Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a...
US-9,608,058 Semiconductor device
A semiconductor device includes a SiC layer that has a first surface and a second surface, a first electrode in contact with the first surface, a first SiC...
US-9,608,057 Semiconductor device and method for manufacturing semiconductor device
A MOS semiconductor device has a MOS structure, including a p.sup.- region that surrounds an n.sup.+-type source region and has a net doping concentration lower...
US-9,608,056 Schottky-barrier device and related semiconductor product
In one general aspect, a power rectifier device can include a drift layer including silicon carbide of n-type conductivity, and a Schottky electrode disposed on...
US-9,608,055 Semiconductor device having germanium active layer with underlying diffusion barrier layer
Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate...
US-9,608,054 Semiconductor device and method for fabricating the same
A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern...
US-9,608,053 EL display panel, power supply line drive apparatus, and electronic device
Disclosed herein is an electroluminescence display panel including a pixel circuit, a signal line, a scan line, a drive power supply line, a common power supply...
US-9,608,052 Sub-pixel arrangement, method for repairing the same, display panel and display device
The present disclosure provides a sub-pixel arrangement including: a first sub-pixel region, a second sub-pixel region, and a connection region. Each electrode...
US-9,608,051 Display apparatus, manufacturing method of display apparatus, and electronic device
A display apparatus including: a display region provided with a plurality of pixel portions; wires installed to the respective pixel portions within the display...
US-9,608,050 Organic light emitting diode display utilizing a curved semiconductor layer
An organic light emitting diode (OLED) display including: a substrate; a semiconductor layer disposed on the substrate and including a switching semiconductor...
US-9,608,049 Organic light emitting diode display
An organic light emitting diode (OLED) display includes a flexible substrate, a barrier layer disposed on the flexible substrate, and an organic light emitting...
US-9,608,048 Touch display device and method for manufacturing the same
A touch display device and a method for manufacturing the same are provided. The touch display device includes a first substrate, a second substrate disposed...
US-9,608,047 Integrated touch screen
In one embodiment, an apparatus includes a display stack for a touch-sensitive screen. The display stack comprises a plurality of layers in which a top layer...
US-9,608,046 Organic light emitting diode display having quantum dot
The present disclosure relates to an organic light emitting diode display having a quantum dot. The present disclosure suggests an organic light emitting diode...
US-9,608,045 Display device
A display device includes a first substrate, an organic EL layer formed on the first substrate and curved in each pixel, and color filters disposed in the...
US-9,608,044 OLED display panel, method for manufacturing the same, display device and electronic product
The present disclosure provides an OLED display panel, which sequentially includes: a first light emitting layer covering at least two adjacent sub-pixels...
US-9,608,043 Method of operating memory array having divided apart bit lines and partially divided bit line selector switches
A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by...
US-9,608,042 Electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated...
Embodiments of the present disclosure describe electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated...
US-9,608,041 Semiconductor memory device and method of manufacturing the same
A semiconductor memory device comprising a bit line extending in a first direction, a vertical gate cell including a gate oxide layer and a gate metal layer...
US-9,608,040 Memory device and method of fabricating the same
A memory device including a substrate, an insulating layer on the substrate, the insulating layer including a first region having a first top surface and a...
US-9,608,039 Magnetic junctions programmable using spin-orbit interaction torque in the absence of an external magnetic field
A magnetic memory including a plurality of magnetic junctions and at least one spin-orbit interaction (SO) active layer is described. Each of the magnetic...
US-9,608,038 Magnetic tunnel junction (MTJ) memory element having tri-layer perpendicular reference layer
The present invention is directed to an STT-MRAM device comprising a plurality of memory elements. Each of the memory elements includes an MTJ structure in...
US-9,608,037 Mesa structure diode with approximately plane contact surface
There is provided an electronic device including at least two diodes each having a mesa structure, including: a first and a second doped semiconductor portion...
US-9,608,036 Solid-state imaging device, with charge holding section between trenched transfer gate sections manufacturing...
A solid-state imaging device includes a pixel having a photoelectric conversion element which generates a charge in response to incident light, a first transfer...
US-9,608,035 Method of wafer-scale integration of semiconductor devices and semiconductor device
The method of wafer-scale integration of semiconductor devices comprises the steps of providing a semiconductor wafer (1), a further semiconductor wafer (2),...
US-9,608,034 Manufacturing method of back illumination CMOS image sensor device using wafer bonding
Disclosed is a manufacturing method of a semiconductor device including a step of attaching semiconductor wafers together, in which it is prevented that the...
US-9,608,033 Solid-state image sensor, method of manufacturing the same, and camera
A solid-state image sensor includes a pixel area and a peripheral circuit area. The pixel area includes a first MOS, and the peripheral circuit area includes a...
US-9,608,032 Backside illumination (BSI) image sensor and manufacturing method thereof
A method for manufacturing a BSI image sensor includes following steps: A substrate is provided. The substrate includes a front side and a back side opposite to...
US-9,608,031 Method for manufacturing solid-state image sensor
A method for manufacturing a solid-state image sensor, the method comprising preparing a substrate including a photoelectric conversion portion, forming, on the...
US-9,608,030 Solid-state imaging apparatus, method of manufacturing the same, and electronic apparatus
A solid-state imaging apparatus includes an imaging region in which pixels are arranged, a connection region that surrounds the imaging region and includes an...
US-9,608,029 Optical package with recess in transparent cover
Embodiments of the present invention are directed to optical packages having a cover made of transparent material with a recess formed therein and methods of...
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