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Patent # Description
US-9,607,978 ESD-protection circuit for integrated circuit device
A double-diffused metal oxide semiconductor (DMOS) structure is configured as an open drain output driver having electrostatic discharge (ESD) protection and a...
US-9,607,977 Electrostatic discharge protection device and method for producing an electrostatic discharge protection device
An electrostatic discharge protection device includes an anode, a cathode, a negative voltage holding transistor and a positive voltage holding transistor. The...
US-9,607,976 Electrostatic discharge protection device
An ESD protection device including a Si substrate with an ESD protection circuit formed at the surface of the substrate; pads formed on the Si substrate; a...
US-9,607,975 Semiconductor device and wireless tag using the same
In a wireless tag with which a wireless communication system whose electric power of a carrier wave from a R/W is high, an overvoltage protection circuit is...
US-9,607,974 Package structure and fabrication method thereof
A method for fabricating a package structure is provided, which includes: providing a first carrier having a circuit layer thereon; forming a plurality of...
US-9,607,973 Method for establishing interconnects in packages using thin interposers
A method of interconnecting first and second semiconductor dies is provided. A splice interposer is attached to a top surface of a substrate through first...
US-9,607,972 Optical module
To suppress appearance of a ghost. The present optical module includes a sensor configured to pick up an image of an image pickup object, and a memory chip...
US-9,607,971 Semiconductor device and sensing system
A semiconductor device includes a first substrate that has a sensing portion that detects predetermined information, a second substrate that has a first...
US-9,607,970 Light-emitting device having a plurality of concentric light transmitting areas
The light-emitting device of the present invention includes LED chips provided on a ceramic substrate and a sealing material in which the LED chips are...
US-9,607,969 Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and...
A package can include a plurality of semiconductor devices stacked in a first direction and commonly sharing at least a first reference potential and a data...
US-9,607,968 Flexible packages including chips
A flexible package may be provided. The flexible package may include a flexible molding member including a top surface. The flexible package may include a first...
US-9,607,967 Multi-chip semiconductor package with via components and method for manufacturing the same
A multi-chip semiconductor package includes a lower RDL interposer, a first chip on the lower RDL interposer within a chip mounting area, via components mounted...
US-9,607,966 Chip arrangement
A chip arrangement is provided. The chip arrangement includes: a first chip electrically connected to the first chip carrier top side; a second chip...
US-9,607,965 Semiconductor device and method of controlling warpage in reconstituted wafer
A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality...
US-9,607,964 Method and materials for warpage thermal and interconnect solutions
Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top...
US-9,607,963 Semiconductor device and fabrication method thereof
A semiconductor device is disclosed, which includes: a substrate having a substrate body and a plurality of conductive pads formed on the substrate body,...
US-9,607,962 Semiconductor device and manufacturing method thereof
A semiconductor device includes a corner constituted by a first side and a second side being perpendicular to the first side; and a plurality of pads including...
US-9,607,961 Semiconductor device
A semiconductor device includes a semiconductor substrate, a front surface electrode provided on a front surface of the semiconductor substrate, a solder layer,...
US-9,607,960 Bonding structure and flexible device
A bonding structure comprising a contact pad, an anisotropic conductive film (ACF) and a contact structure is provided. The contact pad includes at least one...
US-9,607,959 Packaging device having plural microstructures disposed proximate to die mounting region
An example packaging device includes a substrate having an integrated circuit die mounting region disposed thereon. A plurality of microstructures are disposed...
US-9,607,958 Semiconductor device and method for forming openings and trenches in insulating layer by first LDA and second...
A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength...
US-9,607,957 Semiconductor device
A semiconductor chip includes a substrate, an electrode pad formed on the substrate, an insulating layer covering the substrate and the electrode pad, and...
US-9,607,956 Semiconductor device and method of manufacturing the same
A semiconductor device in which reliability of a bonding pad to which a conductive wire is bonded is achieved. A bonding pad having an OPM structure is formed...
US-9,607,955 Contact pad
The present disclosure relates to forming multi-layered contact pads for a semiconductor device, wherein the various layers of the contact pad are formed using...
US-9,607,954 Method of manufacturing semiconductor device and semiconductor device
Object is to prevent a coupling failure between a rewiring and a coupling member for coupling to outside. A passivation film and a first polyimide film are...
US-9,607,953 Semiconductor package with isolation wall
A semiconductor device package includes an isolation wall located between a first circuit and a second circuit on a substrate. The isolation wall is configured...
US-9,607,952 High-z oxide nanoparticles embedded in semiconductor package
A method includes embedding high-z oxide nanoparticles in a semiconductor package of a semiconductor packaged assembly, wherein the high-z nanoparticles are...
US-9,607,951 Chip package
According to an embodiment of the present invention, a chip package is provided. The chip package includes a substrate. A chip is disposed on the substrate. A...
US-9,607,950 Package substrate and semiconductor package including the same
There is provided a package substrate including: a body unit including a plurality of base substrates and having a mounting region allowing at least one...
US-9,607,949 Semiconductor device having semiconductor chips in resin and electronic circuit device with the semiconductor...
A semiconductor device includes a first semiconductor unit including a plurality of first semiconductor chips, an organic resin provided between the first...
US-9,607,948 Method and circuits for communication in multi-die packages
Various example implementations are directed to circuits and methods for inter-die communication on a multi-die integrated circuit (IC) package. According to an...
US-9,607,947 Reliable microstrip routing for electronics components
Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having...
US-9,607,946 Reverse damascene process
The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding...
US-9,607,945 Semiconductor device comprising power elements in juxtaposition order
A semiconductor device including a multiplicity of large current power elements with each power element divided into a multiplicity of divisional elements and...
US-9,607,944 Efficient layout placement of a diode
A semiconductor device includes a plurality of first wires and second wires, a first conductive layer, and a second conductive layer. Each of the first wires...
US-9,607,943 Capacitors
Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between...
US-9,607,942 Semiconductor device with patterned ground shielding
Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS)...
US-9,607,941 Conductive via structure and fabrication method thereof
A method for fabricating a conductive via structure is provided, which includes the steps of: forming in an encapsulant a plurality of openings penetrating...
US-9,607,940 Semiconductor device
A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and...
US-9,607,939 Semiconductor package and method of fabricating the same
A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor...
US-9,607,938 Integrated circuit packaging system with embedded pad on layered substrate and method of manufacture thereof
An integrated circuit packaging system and method of manufacture thereof includes: a dielectric core having an embedded pad; a top solder resist layer on the...
US-9,607,937 Pin grid interposer
An interposer to form a frame around a bottom chip bonded to a package substrate and to standoff a top chip or package for clearance of the bottom chip. The...
US-9,607,936 Copper bump joint structures with improved crack resistance
An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a semiconductor substrate, and a copper bump...
US-9,607,935 Semiconductor chip package with undermount passive devices
Various semiconductor chip packages with undermounted passive devices and methods of making the same are disclosed. In one aspect, a method of manufacturing is...
US-9,607,934 Lead frame, lead frame with resin attached thereto, resin package, light emitting device, and method for...
A lead frame includes at least one row of a plurality of unit regions arranged in a first direction. Each of the unit regions includes: a first lead; a second...
US-9,607,933 Lead frame structure for quad flat no-lead package, quad flat no-lead package and method for forming the lead...
A lead frame structure for quad flat no-lead (QFN) package includes a main base, a plurality of terminals and a first metal layer. The main base has a center...
US-9,607,932 Semiconductor device
A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is...
US-9,607,931 Semiconductor device for suppressing a temperature increase in beam leads
Provided is a semiconductor device that can suppress a temperature increase in beam leads while reducing the number of wiring lines and can suppress an increase...
US-9,607,930 Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are...
US-9,607,929 Tsv wafer with improved fracture strength
A method including forming a through-substrate via through a thickness of a substrate, the thickness of the substrate is measured from a front side of the...
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