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Patent # Description
US-9,607,928 Method and structures for via substrate repair and assembly
A component can include a substrate having an opening extending between first and second surfaces thereof, and an electrically conductive via having first and...
US-9,607,927 Semiconductor device
A semiconductor device includes a semiconductor chip including a semiconductor substrate, an element formed in an element forming region of the semiconductor...
US-9,607,926 Probe pad design to reduce saw defects
An integrated circuit wafer and fabrication method includes a probe pad structure in saw lanes between integrated circuits. The probe pad structure includes a...
US-9,607,925 Semiconductor device for verifying operation of through silicon vias
A semiconductor device may include: a plurality of output paths, which include a plurality of through silicon vias (TSVs), respectively, and suitable for...
US-9,607,924 Power semiconductor module and method for cooling power semiconductor module
The present disclosure relates to a power semiconductor module comprising a printed circuit board (PCB), and to method of cooling such a power semiconductor...
US-9,607,923 Electronic device having a thermal conductor made of silver between a heat sink and an electronic element, and...
An electronic device is provided, which includes an electronic element and a heat dissipating element disposed on the electronic element through a thermal...
US-9,607,922 Semiconductor device and heat-dissipating mechanism
A semiconductor device includes a semiconductor chip which can be a heat-generating semiconductor chip or a semiconductor relay substrate in which an integrated...
US-9,607,921 Package on package interconnect structure
A structure comprises a post passivation interconnect layer formed over a semiconductor substrate, a metal bump formed over the post passivation interconnect...
US-9,607,920 Self-limiting chemical vapor deposition and atomic layer deposition methods
Methods for depositing silicon on a semiconductor or metallic surface include cycling dosing of silane and chlorosilane precursors at a temperature between...
US-9,607,919 Semiconductor device with thin redistribution layers
A semiconductor device with thin redistribution layers is disclosed and may include forming a first redistribution layer on a dummy substrate, electrically...
US-9,607,918 Fan-out wafer level packages containing embedded ground plane interconnect structures and methods for the...
Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs containing Embedded Ground Planes (EGPs) and backside EGP interconnect structures are...
US-9,607,917 Stacked inductor-electronic package assembly and technique for manufacturing same
An embodiment of a circuit includes a circuit module and an inductor disposed over and electrically coupled to the module. Disposing the inductor over the...
US-9,607,916 Encapsulant materials and a method of making thereof
The present disclosure relates generally to encapsulant materials, a method of making thereof and the use thereof for maintaining the electrical and mechanical...
US-9,607,915 Through substrate vias and device
Method of making through-substrate-vias in glass substrates includes providing a first substrate on which a plurality of needles protruding vertically from the...
US-9,607,914 Molded composite enclosure for integrated circuit assembly
Embodiments of the present disclosure are directed toward a molded composite enclosure for an integrated circuit (IC) assembly. In one embodiment, an enclosure...
US-9,607,913 Low power, temperature regulated circuit for precision integrated circuits
Various embodiments provide a temperature regulated circuit. The temperature regulated circuit includes a suspended mass that is positioned in an opening of a...
US-9,607,912 Integrated circuit comprising at least an integrated antenna
An integrated circuit on a substrate includes a peripheral portion that surrounds an active area and is positioned close to a scribe line providing separation...
US-9,607,911 Optical programming of electronic devices on a wafer
A system for programming integrated circuit (IC) dies formed on a wafer includes an optical transmitter that outputs a digital test program as an optical...
US-9,607,910 Limiting adjustment of polishing rates during substrate polishing
A method of controlling polishing includes polishing a region of a substrate at a first polishing rate, measuring a sequence of characterizing values for the...
US-9,607,909 Analysis device, analysis method, film formation device, and film formation method
An analysis device includes an X-ray generation part configured to generate four monochromatic X-rays with different energies to irradiate a sample, an...
US-9,607,908 Method of manufacturing semiconductor device
Provided is a technique capable of uniformizing the characteristics of a film after a plurality of substrates are processed. A method of manufacturing a...
US-9,607,907 Electric-programmable magnetic module and picking-up and placement process for electronic devices
A picking-up and placement process for electronic devices comprising: (a) providing a first substrate having a plurality of electronic devices formed thereon,...
US-9,607,906 Integrated circuit chip with corrected temperature drift
An integrated circuit chip includes trenches at least partially surrounding a critical portion of a circuit that is sensitive to temperature variations. The...
US-9,607,905 Method of measuring breakdown voltage of semiconductor element and method of manufacturing semiconductor element
A method of measuring a breakdown voltage of a semiconductor element includes the steps below. A wafer provided with a plurality of semiconductor elements each...
US-9,607,904 Atomic layer deposition of HfAlC as a metal gate workfunction material in MOS devices
ALD of Hf.sub.xAl.sub.yC.sub.z films using hafnium chloride (HfCl.sub.4) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal...
US-9,607,903 Method for forming field effect transistors
A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin,...
US-9,607,902 Semiconductor structures and fabrication methods thereof
A method for forming a semiconductor structure includes sequentially providing a semiconductor substrate having NFET regions and NFET regions; forming an...
US-9,607,901 Integrated tensile strained silicon NFET and compressive strained silicon-germanium PFET implemented in FINFET...
A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The...
US-9,607,900 Method and structure to fabricate closely packed hybrid nanowires at scaled pitch
Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers...
US-9,607,899 Integration of vertical transistors with 3D long channel transistors
A method for integrating a vertical transistor and a three-dimensional channel transistor includes forming narrow fins and wide fins in a substrate; forming a...
US-9,607,898 Simultaneously fabricating a high voltage transistor and a finFET
Forming a semiconductor layer on a semiconductor substrate, a top surface of the semiconductor layer above a fin in a second region is higher than a top surface...
US-9,607,897 Semiconductor device and method for manufacturing the same
A method for manufacturing a semiconductor device is provided with: a step of preparing a semiconductor wafer (22) in a state where the circumference of the...
US-9,607,896 Use of repellent material to protect fabrication regions in semi conductor assembly
A method of preparing semiconductor dies from a semiconductor wafer having a plurality of fabrication regions separated by dicing lines on the top side of the...
US-9,607,895 Silicon via with amorphous silicon layer and fabrication method thereof
A method is provided for fabricating a semiconductor structure. The method includes providing a substrate having an upper surface and a bottom surface; and...
US-9,607,894 Radio-frequency device package and method for fabricating the same
An electronic device package has a base and an electronic device chip mounted on the base. The electronic device chip includes a semiconductor substrate having...
US-9,607,893 Method of forming self-aligned metal lines and vias
Disclosed are embodiments of a method, wherein metal lines and vias of an integrated circuit IC) metal level of are formed without requiring separate cut masks...
US-9,607,892 Method for forming a two-layered hard mask on top of a gate structure
A method for fabricating semiconductor device comprising: providing a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer...
US-9,607,891 Aluminum interconnection apparatus
An aluminum interconnection apparatus comprises a metal structure formed over a substrate, wherein the metal structure is formed of a copper and aluminum alloy,...
US-9,607,890 Stress relieving through-silicon vias
Methods and systems for stress relieving through-silicon vias are disclosed and may include forming a semiconductor device comprising a stress relieving stepped...
US-9,607,889 Forming structures using aerosol jet.RTM. deposition
Method and apparatus for direct writing of passive structures having a tolerance of 5% or less in one or more physical, electrical, chemical, or optical...
US-9,607,888 Integration of ALD barrier layer and CVD Ru liner for void-free Cu filling
Methods for integration of atomic layer deposition (ALD) of barrier layers and chemical vapor deposition (CVD) of Ru liners for Cu filling of narrow recessed...
US-9,607,887 Method of manufacturing semiconductor device
In one embodiment, a method of manufacturing a semiconductor device includes forming a convex portion including an interconnect and a first film above a...
US-9,607,886 Self aligned conductive lines with relaxed overlay
A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the planarizing...
US-9,607,885 Semiconductor device and fabrication method
Various embodiments provide semiconductor devices and fabrication methods. In an exemplary method, a dielectric layer can be formed on a semiconductor...
US-9,607,884 Semiconductor device and method of manufacturing the same
Manufacturing stability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes the steps of: forming an etching...
US-9,607,883 Trench formation using rounded hard mask
A method embodiment includes forming a hard mask over a dielectric layer, patterning the hard mask to form an opening, forming a passivation layer on sidewalls...
US-9,607,882 Semiconductor device and manufacturing method thereof
A semiconductor device includes metal wirings formed in a first interlayer dielectric layer disposed over a substrate, a first insulating layer covering...
US-9,607,881 Insulator void aspect ratio tuning by selective deposition
Disclosed herein is a structure conductive lines disposed in a base layer and separated by a first region. Pillars are each disposed over a respective one of...
US-9,607,880 Silicon-on-insulator substrate and method of manufacturing thereof
A method of manufacturing a silicon-on-insulator (SOI) substrate is provided. The method includes forming an island-shaped insulating layer on a first surface...
US-9,607,879 Process for fabrication of a structure with a view to a subsequent separation
A process for fabrication of a structure includes assembling at least two substrates. At least one of these two substrates is intended to be used in...
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