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Patent # Description
US-9,607,726 Composition comprising silver nanowires
A composition for forming a conductive film. The composition comprises a plurality of nanowires comprising silver; a latex comprising polymer particles; and an...
US-9,607,725 Graphene structure, method for producing the same, electronic device element and electronic device
Provided are a graphene structure and a method for producing the same in which graphene can be patterned with high precision, and thereby microfabrication of...
US-9,607,724 Devices processed using x-rays
Objects undergoing processing by a high resolution x-ray microscope with a high flux x-ray source that allows high speed metrology or inspection of objects such...
US-9,607,723 Ultra thin radiation window and method for its manufacturing
For manufacturing a radiation window for an X-ray measurement apparatus, and etch stop layer is first produced on a polished surface of a carrier. A thin film...
US-9,607,722 Infusion systems including computer-facilitated maintenance and/or operation and methods of use
Methods for setting up, maintaining and operating a radiopharmaceutical infusion system, that includes a radioisotope generator, are facilitated by a computer...
US-9,607,721 Method of separating amorphous iron oxides
A method for separating amorphous iron oxides is provided. The method includes steps of sampling, filtering, dissolving and separating, analyzing the solution...
US-9,607,720 Long life high efficiency neutron generator
The design of a compact, high-efficiency, high-flux capable compact-accelerator fusion neutron generator (FNG) is discussed. FNG's can be used in a variety of...
US-9,607,719 Vacuum chamber for plasma electric generation system
A system and apparatus for controlled fusion in a field reversed configuration (FRC) magnetic topology and conversion of fusion product energies directly to...
US-9,607,718 Semiconductor memory device and test operation method thereof
A semiconductor memory device includes: a word line driving unit suitable for performing activation operations for a plurality of normal word lines and a...
US-9,607,717 Reliability screening of ferroelectric memories in integrated circuits
A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. A reference voltage level is determined...
US-9,607,716 Detecting defective connections in stacked memory devices
A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is...
US-9,607,715 Memory internal comparator testing system
In some embodiments, a system includes a memory testing circuit configured to perform a test of an internal comparator of a memory circuit by performing...
US-9,607,714 Hardware command training for memory using write leveling mechanism
A method of training a command signal for a memory module. The method includes programming a memory controller into a mode where a single bit of an address...
US-9,607,713 Electronic device and method for driving the same
An electronic device includes a semiconductor memory that includes: a first line; a second line intersecting the first line; a memory cell coupled at a cross...
US-9,607,712 Shift register group
A shift register group includes a plurality of series-coupled shift registers each being configured to provide an output signal. The third control signal of a...
US-9,607,711 Semiconductor memory device and operating method thereof
There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory cell array including a...
US-9,607,710 Read-threshold calibration in a solid state storage system
A read-threshold calibration method in a solid state storage system including measuring a threshold voltage distribution of solid state storage elements;...
US-9,607,709 Voltage generator, semiconductor memory device having the same, and method of operating semiconductor memory device
A voltage generator that includes an operation mode determination circuit suitable for determining an active mode or a standby mode based on a chip enable...
US-9,607,708 Voltage mode sensing for low power flash memory
Electrically erasable flash memory and method. The memory has a data storage element and a voltage sensing circuit. The data storage element is configured to...
US-9,607,707 Weak erase prior to read
Techniques are disclosed for accurately sensing memory cells without having to wait for a voltage that creeps up on word line after a sensing operation to die...
US-9,607,706 Semiconductor memory device
A semiconductor memory device includes a first memory bank and a second memory bank; an address counter unit including: a first address counter suitable for...
US-9,607,705 Apparatuses and methods for charging a global access line prior to accessing a memory
Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a...
US-9,607,704 Data reading method, memory controlling circuit unit and memory storage device
A data reading method is provided. The data reading method includes receiving a read command from a host system; sending a first read command sequence to obtain...
US-9,607,703 Memory system
According to one embodiment, a memory system includes a memory and a setting unit. The memory includes a memory cell array and a peripheral circuit. The memory...
US-9,607,702 Sub-block page erase in 3D p-channel flash memory
A NAND array includes blocks of memory cells. A block of memory cells includes a plurality of strings having channel lines between first and second string...
US-9,607,701 Systems and methods for dynamically programming a flash memory device
The present inventions are related to systems and methods for storing data, and more particularly to systems and methods for writing data to a storage device.
US-9,607,700 Non-volatile memory device, memory system, and methods of operating the device and system
The method of operating a non-volatile memory device includes dumping data stored in input latches of a page buffer to other latches of the page buffer to...
US-9,607,699 Memory system including semiconductor memory device and operating method thereof
An operating method of a memory system including first and second one half pages includes acquiring first and second partial data from main data; performing a...
US-9,607,698 Semiconductor memory device and operating method thereof
A semiconductor memory device may include a plurality of memory cells programmed to have one of first to N.sup.th program states differentiated according to...
US-9,607,697 Non-volatile semiconductor memory device and improved verification and programming method for the same
Provided herein are semiconductor memory devices and operating methods thereof. A semiconductor memory device may include a memory cell array including a...
US-9,607,696 Minimal maximum-level programming
A method for writing data, the method may include evaluating current levels of multiple memory cells that belong to a certain set of memory cells or receiving...
US-9,607,695 Multi-bit non-volatile random-access memory cells
Multi-bit non-volatile random access memory cells are disclosed. A multi-bit non-volatile random access memory cell may include a volatile storage element and a...
US-9,607,694 Semiconductor memory device and method of controlling the same
A semiconductor memory device according to the embodiments includes a first wiring, a second wiring that extends to intersect with the first wiring, a memory...
US-9,607,693 Semiconductor storage device
A semiconductor storage device according to the present embodiments includes a first bit line and a first word line. A resistance-change memory element is...
US-9,607,692 Threshold voltage distribution determination
Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to...
US-9,607,691 Memory cell architecture for multilevel cell programming
Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary...
US-9,607,690 High sum-rate write-once memory
Provided are modified one-hot (MOH) constructions for WOM codes with low encoding and decoding complexity, that achieve high sum-rates. Features include...
US-9,607,689 Solid hard disk and charging/discharging control method for flash chip
A method comprises steps of mapping a same physical page to two mutually coupled logic pages, one logic page being formed by mapping the least significant bit...
US-9,607,688 Memory system including nonvolatile memory and memory controller and programming method for programming data...
According to example embodiments, a nonvolatile memory includes a plurality of memory cells and a plurality of bit lines respectively connected to the plurality...
US-9,607,687 Dual-port static random access memory (SRAM)
In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access...
US-9,607,686 Semiconductor memory device
A semiconductor memory device includes data path circuits and control circuits alternately disposed along a first direction. A first metal layer is disposed on...
US-9,607,685 Memory array with strap cells
A memory array comprises a plurality of memory cells arranged in columns and rows. The memory array also comprises a plurality of first-type strap cells...
US-9,607,684 Circuit-level abstraction of multigate devices using two-dimensional technology computer aided design
A method for predicting a condition in a circuit under design includes obtaining a set comprising first static noise margin curve for the circuit and a second...
US-9,607,683 Emulator for imulating an operation of a SRAM
In some embodiments, a semiconductor device includes an SRAM cell, an emulator and a suppressing device. The SRAM cell, enabled by a word line, includes a first...
US-9,607,682 Address decoding circuit
A decoder is disclosed that is used to select an area of address space in an Integrated Circuit. The decoder uses a hardware shifting module that performs shift...
US-9,607,681 Memory device that supports multiple memory configurations
A memory device comprises: a plurality of memory configuration modes; an option selection logic for selecting one of the plurality of memory configuration modes...
US-9,607,680 EDRAM/DRAM fabricated capacitors for use in on-chip PMUS and as decoupling capacitors in an integrated...
One or more integrated circuits including at least one integrated circuit that is fabricated in a DRAM fabrication process. Capacitors in the DRAM-fabricated...
US-9,607,679 Refresh control device
A refresh control device is disclosed, which relates to a technology for efficiently storing weak cell refresh addresses. The refresh control device includes a...
US-9,607,678 Semiconductor memory device and memory system including same
A method of operating a semiconductor memory device is provided as follows. The semiconductor memory device receive a bank address for a first bank including a...
US-9,607,677 Apparatuses for resetting an address counter during refresh operations
An example apparatus includes an address counter configured to provide refresh addresses to a refresh circuit, wherein the address counter includes a plurality...
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