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Patent # Description
US-9,606,967 Tracing a document in an electronic publication
A system and method for tracing an electronic document within a publication. A message is associated with the electronic document as an identification thereof....
US-9,606,966 Energy and effort efficient reading sessions
Embodiments of the present invention disclose a method, computer program product, and system for presenting text and figures on a display screen. Formatting, by...
US-9,606,965 Semiconductor device
A semiconductor device includes a plurality of spin units individually including a memory cell configured to store values of spins in an Ising model, a memory...
US-9,606,964 Visual modeller for mathematical optimization
Embodiments include methods, and computer program products of a visual modeler of mathematical optimization. Aspects include: analyzing requirements of a visual...
US-9,606,963 Evaluating and optimizing a trajectory function
A method for evaluating a trajectory function to be followed by a physical system includes providing the trajectory function; determining a set of sampling...
US-9,606,962 Methods and systems for adapting object locating
A method and device for dynamically altering the signal-space-to-physical-space mapping database of a set of access points for use in localizing of an object,...
US-9,606,961 Instruction and logic to provide vector compress and rotate functionality
Instructions and logic provide vector compress and rotate functionality. Some embodiments, responsive to an instruction specifying: a vector source, a mask, a...
US-9,606,960 Vector indirect element vertical addressing mode with horizontal permute
An example method for placing one or more element data values into an output vector includes identifying a vertical permute control vector including a plurality...
US-9,606,959 Indicating a sending buffer and receiving buffer in a message to use to validate the message in the receiving...
Provided are a computer program product, system, and method for indicating a sending buffer and receiving buffer in a message to use to validate the message in...
US-9,606,958 Collecting and delivering data to a big data machine in a process control system
A device supporting big data in a process plant includes an interface to a communications network, a cache configured to store data observed by the device, and...
US-9,606,957 Electronic device and method of linking a task thereof
A method of linking a task of an electronic device and the electronic device are provided. The method includes determining whether generation of an event...
US-9,606,956 Method and system for providing a tablet swiping calculator function
A listing of data is displayed in a tablet swiping calculator function display with the listing of data including two or more numerical data entries. A...
US-9,606,955 Embedded universal serial bus solutions
Techniques for embedded high speed serial interface methods are described herein. The method includes issuing a single-ended one (SE1) signal on each of a pair...
US-9,606,954 Communicating with MIPI-compliant devices using non-MIPI interfaces
Using relatively inexpensive, external resistor networks, an electronic device, such as an FPGA, can be configured to use non-MIPI interfaces to communicate...
US-9,606,953 Method, apparatus, and computer program product for entering accessory docking mode in USB type C
Method, apparatus, and computer program product embodiments of the invention are disclosed for entering an accessory docking mode. In example embodiments of the...
US-9,606,952 System with speaker, transceiver and related devices
An audio system includes a docking cradle for receiving and supporting a portable device. The docking cradle includes an interface for providing a connection...
US-9,606,951 External electronic device and interface controller and external electronic device control method
An interface controller, coupling a device main body of an external electronic device to a host, is disclosed, which transmits a termination-on signal to the...
US-9,606,950 Verifying runtime switch-over between multiple I/O protocols on shared I/O connection
A verification environment enables verification of runtime switch-over--i.e., a switch-over without restarting the device under test--between multiple I/O...
US-9,606,949 Universal scalable system: on-the-fly system performance conversion via PC-on-a-card and USB for smart devices...
A universal interconnection scheme enables system architecture modularization with a hot-pluggable external computing module, such as a PC-on-a-card device...
US-9,606,948 CAN bus edge timing control for dominant-to-recessive transitions
Structures and methods herein insert one or more parallel "recessive nulling" driver impedances across a controller area network (CAN) bus starting at the time...
US-9,606,947 Apparatus and methods for serial interfaces
Apparatus and methods for serial interfaces are provided. In one embodiment, an integrated circuit operable to communicate over a serial interface is provided....
US-9,606,946 Methods for sharing bandwidth across a packetized bus and systems thereof
A system, method, and computer readable medium for sharing bandwidth among executing application programs across a packetized bus for packets from multiple DMA...
US-9,606,945 Access controller, router, access controlling method, and computer program
The access controller conducts arbitration between first nodes, each of which is attempting to transmit data to any of second nodes as destinations through a...
US-9,606,944 System and method for computer memory with linked paths
A first memory buffer has a first high speed memory channel and a second high speed memory channel. A second memory buffer is connected to the first memory...
US-9,606,943 External storage device with two interfaces
An external storage device includes a memory, a controller, a first interface, a second interface, a first switching module, and a second switching module. The...
US-9,606,942 Packet processing system, method and device utilizing a port client chain
A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a...
US-9,606,941 Instruction and logic for a binary translation mechanism for control-flow security
A processor includes a front end, an execution pipeline, and a binary translator. The front end includes logic to receive an instruction and to dispatch the...
US-9,606,940 Methods and apparatus to utilize a trusted loader in a trusted computing environment
An embodiment includes at least one machine readable medium on which is stored code that, when executed enables a system to initialize a trusted loader enclave...
US-9,606,939 Memory data security
A memory module secures data stored on the memory module. A request for the data from a computer system is received by the memory module. A verification key...
US-9,606,938 Managing caches in storage systems
A method is used in managing caches in storage systems. A set of block entries is reserved in a reserved block entries list of a storage system. The reserved...
US-9,606,937 Cache insertion based on threshold access frequency
Various systems and methods for adjusting threshold access frequency based on cache pressure are disclosed. The threshold access frequency is adjusted based on...
US-9,606,936 Generalized control registers
Methods, systems, and computer readable media generalize control registers in the context of memory address translations for I/O devices. A method includes...
US-9,606,935 Method and apparatus for preventing non-temporal entries from polluting small structures using a transient buffer
A method for preventing non-temporal entries from entering small critical structures is disclosed. The method comprises transferring a first entry from a higher...
US-9,606,934 Matrix ordering for cache efficiency in performing large sparse matrix operations
Mechanisms are provided for performing a matrix operation. A processor of a data processing system is configured to perform cluster-based matrix reordering of...
US-9,606,933 Multi-core apparatus and method for restoring data arrays following a power gating event
An apparatus includes a fuse array and a plurality of cores. The fuse array is programmed with compressed data. Each of the plurality of cores accesses the fuse...
US-9,606,932 Storage device and control method thereof
A storage device includes a magnetic storage unit storing data, a semiconductor storage unit, and a controller configured to determine whether or not to control...
US-9,606,931 Indicating a length of an instruction of a variable length instruction set
Some implementations disclosed herein provide techniques and arrangements for indicating a length of an instruction from an instruction set that has variable...
US-9,606,930 Tape-managed partition support for effective workload allocation and space management
In one embodiment, a system includes a disk cache and a controller configured to create a cache resident partition in the disk cache, the cache resident...
US-9,606,929 Simulated NVRAM
Embodiments of the invention relate to leveraging disk controller cache memory to simulate non-volatile random access memory. At least one logical block address...
US-9,606,928 Memory system
A memory system includes: a memory controller which executes a data access process with an external device using an access unit; a first memory which is...
US-9,606,927 Set selection of a set-associative storage container
A system includes a set-associative storage container and a processor configured to generate a vector that is a random number. Two or more residue functions are...
US-9,606,926 System for pre-fetching data frames using hints from work queue scheduler
A system for pre-fetching a data frame from a system memory to a cache memory includes a processor, a queue manager, and a pre-fetch manager. The processor...
US-9,606,925 Method, apparatus and system for optimizing cache memory transaction handling in a processor
In one embodiment, a processor includes a caching home agent (CHA) coupled to a core and a cache memory and includes a cache controller having a cache pipeline...
US-9,606,924 System and method for supporting fast and deterministic execution and simulation in multi-core environments
The exemplary embodiments described herein relate to supporting fast and deterministic execution and simulation in multi-core environments. Specifically, the...
US-9,606,923 Information processing device with shared memory, memory order guarantee method using counters fence...
An information processing device includes a plurality of processors including an Acquire side processor and a Release side processor, and a shared memory. The...
US-9,606,922 Selection of post-request action based on combined response and input from the request source
A data structure includes a plurality of entries each corresponding to a different systemwide combined response of a data processing system. A particular entry...
US-9,606,921 Granular creation and refresh of columnar data
Techniques are provided for granular load and refresh of columnar data. In an embodiment, a particular data object that contains particular data formatted...
US-9,606,920 Multi-CPU system and computing system having the same
A multi-CPU data processing system, comprising: a multi-CPU processor, comprising: a first CPU configured with at least a first core, a first cache, and a first...
US-9,606,919 Method and apparatus to facilitate shared pointers in a heterogeneous platform
A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous...
US-9,606,918 Methods and systems for dynamically controlled caching
Systems and methods for improving caching mechanisms in a storage system are disclosed. The method includes storing data associated with a write input/output...
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