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Patent # Description
US-9,614,080 Semiconductor device having electrically floating body transistor, semiconductor device having both volatile...
A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in...
US-9,614,079 MOS devices with ultra-high dielectric constants and methods of forming the same
An integrated circuit structure includes a semiconductor substrate, and a gate stack over the semiconductor substrate. The gate stack includes a high-k gate...
US-9,614,078 Metal-oxide field effect transistor having an oxide region within a lightly doped drain region
A semiconductor device and a method for manufacturing the same are provided. A semiconductor device includes a semiconductor substrate and a gate structure...
US-9,614,077 Vertical finfet with strained channel
A vertical transistor including a strained vertical semiconductor material channel pillar and a method of forming the same are provided. A strained vertical...
US-9,614,076 Semiconductor device and method for manufacturing the same
There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main...
US-9,614,075 Semiconductor device
A semiconductor device includes a fin-shaped silicon layer on a silicon substrate, and a first insulating film around the fin-shaped silicon layer. A...
US-9,614,074 Partial, self-biased isolation in semiconductor devices
A device includes a semiconductor substrate, a buried doped isolation layer disposed in the semiconductor substrate to isolate the device, a body region...
US-9,614,073 Semiconductor device, and manufacturing method for same
A semiconductor device that has a source region, a channel region, and a drain region disposed in order from a surface of the semiconductor device in a...
US-9,614,072 Semiconductor device
A semiconductor device includes a first semiconductor region of a first conductivity type, a first electrode, a second electrode, a third electrode, a first...
US-9,614,071 Semiconductor device
A semiconductor device formed on a silicon carbide substrate that has a front surface on which an electrode is provided and a back surface on which an electrode...
US-9,614,070 Field effect transistor with conduction band electron channel and uni-terminal response
A uni-terminal transistor device is described. In one embodiment, an n-channel transistor comprises a first semiconductor layer having a discrete hole level...
US-9,614,069 III-Nitride semiconductors with recess regions and methods of manufacture
A multi-layer semiconductor structure is disclosed for use in III-Nitride semiconductor devices, including a channel layer comprising a first III-Nitride...
US-9,614,068 Semiconductor device and method of fabricating the same
A semiconductor device includes a first active region, a field insulating layer disposed in the first active region, a first nanowire pattern disposed on the...
US-9,614,067 Semiconductor device and method of fabricating same
A semiconductor device comprising: an insulation substrate; an intrinsic semiconductor nanowire formed on the insulation substrate and having both ends doped in...
US-9,614,066 Semiconductor device provided with an IE type trench IGBT
A switching loss is prevented from being deteriorated by suppressing increase in a gate capacitance due to a cell shrink of an IE type trench gate IGBT. A cell...
US-9,614,065 Inhomogeneous power semiconductor devices
A power semiconductor device includes a power transistor including a plurality of transistor cells on a semiconductor die. At least some of the transistor cells...
US-9,614,064 Semiconductor device and integrated circuit
A semiconductor device includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a body...
US-9,614,063 Homoepitaxial tunnel barriers with functionalized graphene-on-graphene and methods of making
This disclosure describes a method of making a tunnel barrier-based electronic device, in which the tunnel barrier and transport channel are made of the same...
US-9,614,062 Semiconductor device and method for manufacturing thereof
In a semiconductor device including a transistor using an oxide semiconductor film, stable electric characteristics can be provided and high reliability can be...
US-9,614,061 Semiconductor device having fin structure that includes dummy fins
A semiconductor device includes: a substrate, a fin-shaped structure on the substrate, and a dummy fin-shaped structure on the substrate and adjacent to the...
US-9,614,060 Nanowire transistor with underlayer etch stops
A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at...
US-9,614,059 Forming conductive STI liners for FinFETs
An integrated circuit device, and a method of forming, including a semiconductor substrate, isolation regions extending into the semiconductor substrate, a...
US-9,614,058 Methods of forming low defect replacement fins for a FinFET semiconductor device and the resulting devices
One illustrative device disclosed herein includes a substrate fin formed in a substrate comprised of a first semiconductor material, wherein at least a sidewall...
US-9,614,057 Enriched, high mobility strained fin having bottom dielectric isolation
Embodiments are directed to a method of enriching and electrically isolating a fin of a FinFET. The method includes forming at least one fin. The method further...
US-9,614,056 Methods of forming a tri-gate FinFET device
One illustrative method disclosed herein includes, among other things, forming a fin that is positioned above and vertically spaced apart from an upper surface...
US-9,614,055 Semiconductor device and method for fabricating the same
A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main...
US-9,614,054 Method of forming a vertical device
According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming...
US-9,614,053 Spacers with rectangular profile and methods of forming the same
A method includes forming a spacer layer on a top surface and sidewalls of a patterned feature, wherein the patterned feature is overlying a base layer, A...
US-9,614,052 Copper contact plugs with barrier layers
A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an...
US-9,614,051 Semiconductor devices and fabrication method thereof
A method for fabricating a semiconductor device includes providing a substrate; and forming at least one dummy gate structure on the substrate. The method also...
US-9,614,050 Method for manufacturing semiconductor devices
The present invention provides a method for manufacturing a semiconductor device, comprising: forming a contact sacrificial pattern on a substrate to cover...
US-9,614,049 Fin tunnel field effect transistor (FET)
A fin tunnel field effect transistor includes a seed region and a first type region disposed above the seed region. The first type region includes a first...
US-9,614,048 Split gate flash memory structure and method of making the split gate flash memory structure
A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a source...
US-9,614,047 Gate contact with vertical isolation from source-drain
A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers...
US-9,614,046 Semiconductor devices with a thermally conductive layer
An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate...
US-9,614,045 Method of processing a semiconductor device and chip package
In various embodiments, a method of processing a semiconductor device may include providing a semiconductor device comprising a contact pad and a polymer layer;...
US-9,614,044 Semiconductor device with current sensor
A semiconductor device includes a semiconductor body. The semiconductor body includes a load transistor part and a sensor transistor part. A first source region...
US-9,614,043 MOSFET termination trench
A method, in one embodiment, can include forming a core trench and a termination trench in a substrate. The termination trench is wider than the core trench. In...
US-9,614,042 Heterojunction tunnel field effect transistor fabrication using limited lithography steps
A structure and method for fabricating a vertical heterojunction tunnel field effect transistor (TFET) using limited lithography steps is disclosed. The...
US-9,614,041 Multi-gate semiconductor devices with improved hot-carrier injection immunity
A semiconductor device includes a substrate having a first dopant type, a first gate electrode and second gate electrode formed over the substrate and spatially...
US-9,614,040 Strained silicon germanium fin with block source/drain epitaxy and improved overlay capacitance
A semiconductor structure is provided including a strained silicon germanium alloy fin that can be employed as a channel material for a FinFET device and having...
US-9,614,039 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a plurality of trench gates provided abreast in a semiconductor substrate; an interlayer insulation film having opening from...
US-9,614,038 Nanowire device and method of manufacturing the same
A method of manufacturing a nanowire device is disclosed. The method includes providing a substrate, wherein the substrate comprises a pair of support pads, a...
US-9,614,037 Nano-ribbon channel transistor with back-bias control
Embodiments of the invention include a method for fabricating a nano-ribbon transistor device and the resulting structure. A nano-ribbon transistor device...
US-9,614,036 Manufacture method of TFT substrate and sturcture thereof
The present invention provides a manufacture method of an oxide semiconductor TFT substrate, and the method comprises steps of: 1, forming a gate (2) on a...
US-9,614,035 Semiconductor device
A semiconductor device includes a fin protruding from a substrate and extending in a first direction, first and second gate structures intersecting the fin, a...
US-9,614,034 Semiconductor structure and method for fabricating the same
The present invention provides a semiconductor structure, including a substrate, having a recess disposed therein, an insulating layer filled in the recess and...
US-9,614,033 Semiconductor device including an isolation structure and method of manufacturing a semiconductor device
An embodiment of a semiconductor device comprises a first load terminal contact area at a first side of a semiconductor body. A second load terminal contact...
US-9,614,032 Semiconductor device, integrated circuit and method for manufacturing the semiconductor device
A semiconductor device comprises a transistor in a semiconductor body having a first main surface and a second main surface, the first main surface being...
US-9,614,031 Methods for forming a high-voltage super junction by trench and epitaxial doping
A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring...
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