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Patent # Description
US-9,613,978 Methods of forming semiconductor constructions
Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically...
US-9,613,977 Differential etch of metal oxide blocking dielectric layer for three-dimensional memory devices
A method of manufacturing a semiconductor structure includes forming a stack of alternating layers comprising insulating layers and spacer material layers over...
US-9,613,976 Three-dimensional semiconductor memory device
In general, according to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a memory film, a...
US-9,613,975 Bridge line structure for bit line connection in a three-dimensional semiconductor device
A structure is formed on a substrate, which includes a stack of alternating layers comprising insulating layers and electrically conductive layers and a...
US-9,613,974 Semiconductor device and method for manufacturing the same
According to one embodiment, the contact electrode extends in the inter-layer insulating layer toward the second semiconductor region. The metal silicide film...
US-9,613,973 Memory having a continuous channel
The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack...
US-9,613,972 Method of manufacturing semiconductor device
In an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include forming a pattern group on a substrate, the substrate...
US-9,613,971 Select gates with central open areas
A NAND flash memory array includes a select line having a first edge region containing a first portion of floating gate material and a second edge region...
US-9,613,970 Semiconductor nonvolatile memory element
A semiconductor nonvolatile memory element is used to form a constant current source in a semiconductor integrated circuit device. The semiconductor nonvolatile...
US-9,613,969 Semiconductor structure and method of forming the same
The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric...
US-9,613,968 Cross-coupled thyristor SRAM semiconductor structures and methods of fabrication
A memory cell based upon thyristors for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented...
US-9,613,967 Memory device and method of fabricating the same
A method of fabricating a memory device includes providing a substrate having a first region and a second region. A first dielectric layer is formed on the...
US-9,613,966 Semiconductor device
A semiconductor device includes a semiconductor substrate including a plurality of active areas, a bit line crossing the plurality of active areas, a direct...
US-9,613,965 Embedded transistor
An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate...
US-9,613,964 Semiconductor device including a memory cell
A semiconductor device including a non-volatile memory cell including a writing transistor which includes an oxide semiconductor, a reading transistor which...
US-9,613,963 Dual material finFET on single substrate
A semiconductor device and a method for fabricating the device are provided. The semiconductor device has a substrate having a first device region and a second...
US-9,613,962 Fin liner integration under aggressive pitch
A method of forming a fin liner and the resulting device are provided. Embodiments include forming silicon (Si) fins over negative channel field-effect...
US-9,613,961 Field-effect transistor and semiconductor device
According to one embodiment, a field-effect transistor includes a source region of a first conductivity type, a drain region of the first conductivity type and...
US-9,613,960 Fin field effect transistors and fabrication method thereof
A method for forming FinFETs includes providing a semiconductor substrate having at least a first fin in a first region and at least a second fin in a second...
US-9,613,959 Method of forming metal gate to mitigate antenna defect
The present disclosure relates to methods of forming a field effect transistor (FET) over a substrate, and associated integrated circuit device that improve...
US-9,613,958 Spacer chamfering gate stack scheme
A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are...
US-9,613,957 Semiconductor device and method for manufacturing the same
A semiconductor device includes a first active region including at least one first recess; a second active region including at least one second recess; an...
US-9,613,956 Self-aligned punchthrough stop doping in bulk finFET by reflowing doped oxide
A technique relates to punchthrough stop (PTS) doping in bulk fin field effect transistors. Fins are formed on a substrate, and each pair of the fins has a fin...
US-9,613,955 Hybrid circuit including a tunnel field-effect transistor
The present invention relates generally to integrated circuits and more particularly, to a structure and method of forming a hybrid circuit including a tunnel...
US-9,613,954 Selective removal of semiconductor fins
An array of semiconductor fins is formed on a top surface of a substrate. A dielectric material liner is formed on the surfaces of the array of semiconductor...
US-9,613,953 Semiconductor device, semiconductor device layout, and method of manufacturing semiconductor device
A layout of a semiconductor device is stored on a non-transitory computer-readable medium. The layout includes an active area region extending in a first...
US-9,613,952 Semiconductor ESD protection device
A semiconductor device includes high-voltage (HV) and low-voltage (LV) MOS's formed in a substrate. The HV MOS includes a first semiconductor region having a...
US-9,613,951 Semiconductor device with diode
According to one embodiment, a semiconductor device includes a first and second electrode, a first, second, third and fourth semiconductor region, and a first...
US-9,613,950 Semiconductor device
In a semiconductor device including an IGBT and a diode, an upper-side lifetime control region, which is provided in the drift region within a range located...
US-9,613,949 Bipolar junction transistor and diode
A bipolar junction transistor (BJT) and a diode including fin structures are provided in the present invention. In the BJT and the diode of the present...
US-9,613,948 Electrostatic discharge protection semiconductor device
An ESD protection semiconductor device includes a substrate, a first isolation structure formed in the substrate, a gate disposed on the substrate, a source...
US-9,613,947 Monolithic microwave integrated circuit (MMIC) cascode connected transistor circuit
A cascode transistor circuit having an active region, the active region having a source, a drain, a floating source/drain, a first gate disposed between the...
US-9,613,946 Low voltage triggered silicon controlled rectifier with high holding voltage and small silicon area
A semiconductor device includes a P-type semiconductor substrate, a first N-well, a second N-well, and a P-well adjoining the first and second N-wells, a first...
US-9,613,945 Semiconductor device and method of manufacturing semiconductor device
A diffusion diode including a p.sup.+ diffusion region, a p-type diffusion region, and an n.sup.+ diffusion region is formed in the front surface of a...
US-9,613,944 Semiconductor device and switching circuit
A semiconductor device includes: a main switching element, a current-sensing switching element and a surge protection element, which are formed on a single...
US-9,613,943 Semiconductor device having output buffers and voltage path coupled to output buffers
An apparatus includes first and second data pads arranged adjacently to each other in a first direction without an intervention of a pad therebetween, first and...
US-9,613,942 Interposer for a package-on-package structure
A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an...
US-9,613,941 Exposed die power semiconductor device
A semiconductor package has a lead frame and a power die. The lead frame has a first die paddle with a cavity formed entirely therethrough. The power die, which...
US-9,613,940 Carrier array and light emitting diode package
A carrier array adapted for carrying a plurality of chips is provided. The carrier array includes a lead frame, controllers and first packages. The lead frame...
US-9,613,939 Opto-electronic modules including features to help reduce stray light and/or optical cross-talk
Opto-electronic modules, which can be fabricated in a wafer-scale process, include light emitting and/or light sensing devices mounted on or in a substrate. The...
US-9,613,938 Module and method for manufacturing the module
A module includes a first substrate including first electrodes; a first element bonded to the first substrate, and including second electrodes disposed at a...
US-9,613,937 LED module
An LED module 100 includes LED chips 21, 22 spaced apart from each other, and an LED chip 23 offset from a straight line connecting the LED chips 21 and 22 and...
US-9,613,936 LED module including an LED
An LED module includes a carrier plate having an arrangement face and a wall on the upper side of the plate, the wall running peripherally around the...
US-9,613,935 LED module
An LED module includes a substrate, one or more LED chips supported by a main surface of the substrate, and wirings. The substrate has one or more through holes...
US-9,613,934 Interconnect structures with polymer core
Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit...
US-9,613,933 Package structure to enhance yield of TMI interconnections
An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound...
US-9,613,932 Integrated circuit package and method of making same
A chip package includes a first die with an active surface having at least one die pad positioned thereon; a first adhesive layer having a first surface coupled...
US-9,613,931 Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
An embodiment package includes a first fan-out tier, fan-out redistribution layers (RDLs) over the first fan-out tier, and a second fan-out tier over the...
US-9,613,930 Semiconductor device and method for manufacturing a semiconductor device
A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a...
US-9,613,929 Power semiconductor chip with a metallic moulded body for contacting thick wires or strips and method for the...
The invention relates to a power semiconductor chip (10) having at least one upper-sided potential surface and contacting thick wires (50) or strips, comprising...
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