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Patent # Description
US-9,613,928 Method and apparatus for chip-to-wafer integration
An apparatus and a method for chip-to-wafer integration is provided. The apparatus includes a coating module, a bonding module and a cleaning module. The method...
US-9,613,927 Semiconductor device and method for manufacturing semiconductor device
A method includes the steps of: preparing a lead frame including a plurality of die pads, and preparing a plurality of semiconductor chips; disposing each of...
US-9,613,926 Wafer to wafer bonding process and structures
Bonded structures and method of forming the same are provided. A conductive layer is formed on a first surface of a bonded structure, the bonded structure...
US-9,613,925 Method for bonding semiconductor devices on sustrate and bonding structure formed using the same
The present invention provides a bonding method in semiconductor manufacturing process and a bonding structure formed using the same, which can achieve...
US-9,613,924 Method of flip-chip assembly of two electronic components by UV annealing, and assembly obtained
The invention concerns a method of flip-chip assembly between first (1) and second (2) components each comprising connection pads (11, 21) on one of the faces...
US-9,613,922 Semiconductor device and manufacturing method thereof
Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon...
US-9,613,921 Structure to prevent solder extrusion
A spacer structure formed adjacent a solder connection which prevents solder extrusion and methods of manufacture are disclosed. The method includes forming a...
US-9,613,920 Microelectronic package utilizing multiple bumpless build-up structures and through-silicon vias
A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second...
US-9,613,919 Chip package and method for forming the same
A chip package is provided. The chip package includes a substrate having a first surface and a second surface opposite thereto. A dielectric layer is disposed...
US-9,613,918 RF power multi-chip module package
High power multi-chip module packages for packaging semiconductor dice are disclosed. The disclosed packages have an output power of at least 1 kilowatt (kW)...
US-9,613,917 Package-on-package (PoP) device with integrated passive device in a via
A package for a use in a package-on-package (PoP) device. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the...
US-9,613,916 Protection ring for image sensors
Some embodiments of the present disclosure provide an image sensor. The image sensor includes a pixel sensor array including a plurality of photosensors...
US-9,613,915 Reduced-warpage laminate structure
A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively...
US-9,613,914 Post-passivation interconnect structure
A semiconductor device includes a passivation layer overlying a semiconductor substrate, and an interconnect structure overlying the passivation layer. The...
US-9,613,913 Method of forming electromagnetic interference shielding layer of ball grid array semiconductor package and...
Provided are a method of forming an electromagnetic interference (EMI) shielding layer of a ball grid array (BGA) semiconductor package, and a base tape used in...
US-9,613,912 Method of marking a semiconductor package
A method of making a semiconductor device can include providing a wafer comprising a plurality of semiconductor die, wherein each semiconductor die comprises an...
US-9,613,911 Self-similar and fractal design for stretchable electronics
The present invention provides electronic circuits, devices and device components including one or more stretchable components, such as stretchable electrical...
US-9,613,910 Anti-fuse on and/or in package
A package structure includes an integrated circuit die, a redistribution structure, an anti-fuse, and external connectors. The integrated circuit die is...
US-9,613,909 Methods and devices for metal filling processes
Metal filling processes for semiconductor devices and methods of fabricating semiconductor devices. One method includes, for instance: obtaining a wafer with at...
US-9,613,908 Ultra-thin dielectric diffusion barrier and etch stop layer for advanced interconnect applications
Implementations described herein generally relate to the formation of a silicon and aluminum containing layer. Methods described herein can include positioning...
US-9,613,907 Low resistivity damascene interconnect
A damascene interconnect structure may be formed by forming a trench in an ILD. A diffusion barrier may be deposited on trench surfaces, followed by a first...
US-9,613,906 Integrated circuits including modified liners and methods for fabricating the same
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes...
US-9,613,905 Electronic interconnects and devices with topological surface states and methods for fabricating same
An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having...
US-9,613,904 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a first substrate, a second substrate, a dam layer, a photoresist layer, and a conductive layer. The first substrate has a...
US-9,613,903 Fine line space resolution lithography structure for integrated circuit features using double patterning technology
A hard mask is disposed over a base material, and an I-shaped first opening is disposed in the hard mask. The first opening includes two parallel portions and a...
US-9,613,902 Connections for memory electrode lines
Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line...
US-9,613,901 Electronic device including a semiconductor memory unit that includes cell mats of a plurality of planes...
An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of planes vertically stacked over a substrate. Each plane...
US-9,613,900 Nanoscale interconnect structure
An interconnect structure includes a first dielectric material having an undercut region located at an upper surface thereof. A first conductive structure is...
US-9,613,899 Epitaxial semiconductor fuse for FinFET structure
On-chip, doped semiconductor fuses are formed in FinFET structures using epitaxial growth processes. Recesses are formed in selected portions of the fins...
US-9,613,898 Raised e-fuse
A method of manufacturing a semiconductor device with a fuse is provided including the steps of providing a semiconductor-on-insulator (SOI) structure including...
US-9,613,897 Integrated circuits including magnetic core inductors and methods for fabricating the same
Magnetic core inductors implemented on integrated circuits and methods for fabricating such magnetic core inductors are disclosed. An exemplary magnetic core...
US-9,613,896 Semiconductor memory device with conductive columnar body
A semiconductor memory device according to an embodiment comprises: when three directions intersecting each other are assumed to be first through third...
US-9,613,895 Semiconductor package with double side molding
A semiconductor package includes an RDL interposer having a first side, a second side, and a vertical sidewall extending between the first side and the second...
US-9,613,894 Electronic package
An electronic package is provided. The electronic package includes an insulator having a recessed portion formed therein; an electronic element embedded in the...
US-9,613,893 Wiring substrate and method for manufacturing the same
A wiring substrate includes a first outermost conductor layer, a first outermost insulating layer covering the first conductor layer, a second outermost...
US-9,613,892 Solid state contactor with improved interconnect structure
A printed circuit board for selectively communicating power from a power source to a use has an input bus for receiving a power supply. A transistor is...
US-9,613,891 Electronic packages for flip chip devices
Electronic packages are formed from a generally planar leadframe having a plurality of leads coupled to a GaN-based semiconductor device, and are encased in an...
US-9,613,890 Semiconductor device
A semiconductor device includes a resin package, a semiconductor chip sealed in the package and having first and second pads on a front surface. An island of...
US-9,613,889 Packaged circuit with a lead frame and laminate substrate
Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a...
US-9,613,888 Semiconductor device and semiconductor module
A semiconductor device in the preferred embodiment includes: a lead frame comprising a die pad and an electrode terminal; and at least one semiconductor chip...
US-9,613,887 Semiconductor system, device and structure
An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal...
US-9,613,886 Optical coupling module
An optical coupling module includes a silicon photonic substrate, and an optical waveguide module. The silicon photonic substrate has a first surface and a...
US-9,613,885 Plastic cooler for semiconductor modules
A cooling apparatus includes a plurality of discrete modules and a plastic housing. Each module includes a semiconductor die encapsulated by a mold compound, a...
US-9,613,884 Semiconductor device
Provided is a semiconductor device. The semiconductor device includes a substrate including a cantilever configured to generate a flow of cooling media through...
US-9,613,883 Semiconductor device
[Object] A semiconductor device is configured to release heat from semiconductor chips more efficiently. [Means for Solution]A semiconductor device includes: a...
US-9,613,882 Nanoparticle thermal interface agents for reducing thermal conductance resistance
A thermal interface material (TIM) using high thermal conductivity nano-particles, particularly ones with large aspect ratios, for enhancing thermal transport...
US-9,613,881 Semiconductor device having improved heat-dissipation characteristics
A semiconductor device having improved heat-dissipation characteristics is capable effectively discharging heat that is generated inside the semiconductor...
US-9,613,880 Semiconductor structure and fabrication method thereof
A method for fabricating a semiconductor structure includes: providing a substrate with a dielectric layer and a passivation layer formed on the substrate;...
US-9,613,879 Ultralow power carbon nanotube logic circuits and method of making same
In one embodiment, a complementary metal-oxide-semiconductor (CMOS) logic device formed with single-walled carbon nanotubes (SWCNTs) includes: at least one...
US-9,613,878 Carrier and a method for processing a carrier
According to various embodiments, a carrier may be provided, the carrier including: a hollow chamber spaced apart from a surface of the carrier; a trench...
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