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Patent # Description
US-9,613,877 Semiconductor packages and methods for forming semiconductor package
Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region...
US-9,613,876 Thin film transistor substrate including a channel length measuring pattern and display panel having the same
A thin film transistor (TFT) substrate includes a base substrate, a TFT disposed on the base substrate. The TFT includes a gate electrode, a semiconductor layer...
US-9,613,875 Method and system for manufacturing semiconductor epitaxy structure
A system for manufacturing semiconductor epitaxy structure includes a deposition apparatus, a curvature monitor system and a control unit. The deposition...
US-9,613,874 Methods for evaluating semiconductor device structures
Methods for evaluating semiconductor device structures are provided. In one example, a method includes forming a support layer on a first side of a lamellar...
US-9,613,873 Nanowire semiconductor device
A method for forming a nanowire device comprises depositing a hard mask on portions of a silicon substrate having a <110> orientation wherein the hard...
US-9,613,872 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes forming a first metal containing a first conductivity-type impurity above a substrate provided with a...
US-9,613,871 Semiconductor device and fabricating method thereof
A semiconductor device is provided. A substrate includes a first region and a second region. A first wire pattern, extending in a first direction, is formed at...
US-9,613,870 Gate stack formed with interrupted deposition processes and laser annealing
Semiconductor structures and methods of fabricating the same using interrupted deposition processes and multiple laser anneals are provided. The structure...
US-9,613,869 FinFET devices
FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of...
US-9,613,868 Fin field-effect transistors and fabrication methods thereof
A method for forming FinFETs includes, sequentially, providing a substrate; forming a plurality of fins on a surface of the substrate; forming a gate structure...
US-9,613,867 Symmetric tunnel field effect transistor
The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The...
US-9,613,866 Gate stack formed with interrupted deposition processes and laser annealing
Semiconductor structures and methods of fabricating the same using interrupted deposition processes and multiple laser anneals are provided. The structure...
US-9,613,865 Semiconductor die and die cutting method
The present disclosure provides die cutting methods and semiconductor dies. A semiconductor substrate has a test region, isolation regions, and core regions. A...
US-9,613,864 Low capacitance interconnect structures and associated systems and methods
Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of...
US-9,613,863 Method for forming electroless metal through via
A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface,...
US-9,613,862 Chamferless via structures
Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one self-aligned via within at least dielectric...
US-9,613,861 Damascene wires with top via structures
Damascene wires with top via structures and methods of manufacture are provided. The semiconductor structure includes a damascene wiring structure with an...
US-9,613,860 Method of manufacturing thin-film transistor
According to one embodiment, a method of manufacturing a thin-film transistor includes forming a semiconductor layer on a gate electrode with an insulating...
US-9,613,859 Direct deposition of nickel silicide nanowire
Methods for direct deposition of a metal silicide nanowire for back-end interconnection structures for semiconductor applications are provided. In one...
US-9,613,858 Method and composition for electrodeposition of copper in microelectronics with dipyridyl-based levelers
A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl...
US-9,613,857 Electrostatic discharge protection structure and method
A semiconductor package comprises a top package and a bottom package with a plurality of fan-out interconnect structures. A plurality of inter-package...
US-9,613,856 Method of forming metal interconnection
A method of fabricating a semiconductor device is disclosed. The method includes forming a first conductive feature over a substrate, forming a dielectric layer...
US-9,613,855 Methods of forming MIS contact structures on transistor devices in CMOS applications
A method that includes, among other things, forming first and second contact openings in a layer of insulating material that respectively expose a portion of...
US-9,613,854 Method and apparatus for back end of line semiconductor device processing
A method of forming a device may include: forming an opening through a dielectric layer and an underlying etching stop layer to expose a metal line. The method...
US-9,613,853 Copper wire and dielectric with air gaps
Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening...
US-9,613,852 Semiconductor structure and method making the same
The present disclosure provides a method for forming a semiconductor structure. In accordance with some embodiments, the method includes providing a substrate...
US-9,613,851 Method for manufacturing interconnect structures incorporating air gap spacers
A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down...
US-9,613,850 Lithographic technique for feature cut by line-end shrink
A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset...
US-9,613,849 Composite substrate manufacturing method, and composite substrate
Disclosed is a composite substrate manufacturing method whereby, after bonding a semiconductor substrate (1) and a supporting substrate (3) to each other, the...
US-9,613,848 Dielectric structures with negative taper and methods of formation thereof
A method for forming a dielectric structure includes forming an auxiliary layer over a substrate, and forming a hole within the auxiliary layer. A fill material...
US-9,613,847 Integration of shallow trench isolation and through-substrate vias into integrated circuit designs
A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the...
US-9,613,846 Pad design for electrostatic chuck surface
Embodiments are directed to an electrostatic chuck surface having minimum contact area features. More particularly, embodiments of the present invention provide...
US-9,613,845 Immersion de-taping
Embodiments using immersion de-taping are described. A substrate having a substrate tape attached thereto is provided. The substrate includes electrically...
US-9,613,844 3D semiconductor device having two layers of transistors
A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and...
US-9,613,843 Power overlay structure having wirebonds and method of manufacturing same
A power overlay (POL) structure includes a power device having at least one upper contact pad disposed on an upper surface of the power device, and a POL...
US-9,613,842 Wafer handler and methods of manufacture
A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed...
US-9,613,841 Area array semiconductor device package interconnect structure with optional package-to-package or flexible...
An area array integrated circuit (IC) package for an IC device. The IC package includes a first substrate with conductive traces electrically coupled to the IC...
US-9,613,840 Apparatus and method for bonding substrates
This invention relates to a method and a device for temporary bonding of a first substrate with a second substrate. The device is comprised of a mounting...
US-9,613,839 Control of workpiece temperature via backside gas flow
A system and method for modulating and controlling the localized temperature of a workpiece during processing is disclosed. The system uses a platen having one...
US-9,613,838 Batch-type vertical substrate processing apparatus and substrate holder
A batch-type vertical substrate processing apparatus includes a processing chamber into which a substrate holder configured to stack and hold a plurality of...
US-9,613,837 Substrate processing apparatus and maintenance method thereof
A substrate processing apparatus includes: a first processing chamber; a second processing chamber; a transfer chamber; a frame structure; and an elevating...
US-9,613,836 Coating film forming apparatus, coating film forming method, and recording medium
A coating film forming apparatus includes: a substrate holding unit to horizontally hold a substrate; a rotating mechanism to rotate the substrate held by the...
US-9,613,835 Heating lamp assembly
Embodiments of heating lamps and heating lamp assemblies are disclosed herein. In some embodiments, a heating lamp may include a bulb; a reflector...
US-9,613,834 Replaceable upper chamber section of plasma processing apparatus
A replaceable upper chamber section of a plasma reaction chamber in which semiconductor substrates can be processed comprises a monolithic metal cylinder having...
US-9,613,833 Methods and apparatus for wetting pretreatment for through resist metal plating
Disclosed are pre-wetting apparatus designs and methods for cleaning solid contaminants from substrates prior to through resist deposition of metal. In some...
US-9,613,832 Mold release film and process for producing semiconductor package
A mold release film to be disposed on a cavity surface of a mold in a method for producing a semiconductor package wherein a semiconductor element is disposed...
US-9,613,831 Encapsulated dies with enhanced thermal performance
The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip...
US-9,613,830 Fully molded peripheral package on package device
A method of making a semiconductor device can include providing a temporary carrier with a semiconductor die mounting site, and forming conductive interconnects...
US-9,613,829 Method for fabricating semiconductor package and semiconductor package using the same
Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the...
US-9,613,828 Method of laser annealing a semiconductor wafer with localized control of ambient oxygen
Laser annealing of a semiconductor wafers using a forming gas for localized control of ambient oxygen gas to reduce the amount of oxidization during laser...
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