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Patent # Description
US-9,613,727 Quasi-neutral plasma generation of radioisotopes
Methods and apparatus for synthesizing radiochemical compounds are provided. The methods include generating a quasi-neutral plasma jet, and directing the plasma...
US-9,613,726 Systems and methods for reducing the storage time of spent nuclear fuel
Systems and methods are provided for reducing the storage time of spent nuclear fuel. In one embodiment, a method is provided that includes providing a sample...
US-9,613,725 Neutron detection apparatus
A neutron detector detects a neutron flux distribution of the inside of a reactor. The neutron detector includes a thimble guide tube that is inserted inside of...
US-9,613,724 Nuclear fuel provided with a coating
This invention relates to a method of preparing a nuclear fuel including the step of depositing a coating which includes fluorine, or at least one compound...
US-9,613,723 Compact nuclear power generation system
A compact nuclear power generation system includes a reactor (3) comprising a core (2) which uses metal fuel containing either or both of uranium-235/238 and...
US-9,613,722 Method and apparatus for reverse memory sparing
An apparatus and method are described for performing forward and reverse memory sparing operations. For example, one embodiment of a processor comprises memory...
US-9,613,721 Semiconductor memory capable of performing through-chip via test and system using the same
A semiconductor memory may include a plurality of stacked semiconductor chips which are interconnected using through-chip vias. The semiconductor memory may set...
US-9,613,720 Semiconductor storage device
A semiconductor storage device has a memory cell array, a plurality of word lines, a plurality of bit lines, and a plurality of blocks including a group of at...
US-9,613,719 Multi-chip non-volatile semiconductor memory package including heater and sensor elements
A method of healing a plurality of non-volatile semiconductor memory devices on a multi-chip package is disclosed. The multi-chip package can be heated to a...
US-9,613,718 Detection system for detecting fail block using logic block address and data buffer address in a storage tester
Disclosed is a detection system for detecting fail block using logic block address and data buffer address in a storage tester, which is capable of comparing...
US-9,613,717 Error correction circuit and semiconductor memory device including the same
An error correction circuit includes: a failure detection unit suitable for detecting failed data among a plurality of data; a data output control unit suitable...
US-9,613,716 Semiconductor device and semiconductor system including the same
A semiconductor system may include a first semiconductor device including a first pad group. The semiconductor system may include a second semiconductor device...
US-9,613,715 Low-test memory stack for non-volatile storage
The various embodiments described herein include systems, methods and/or devices used to package non-volatile memory. In one aspect, the method includes: (1)...
US-9,613,714 One time programming memory cell and memory array for physically unclonable function technology and associated...
A one time programming memory cell includes a selecting circuit, a first antifuse storing circuit and a second antifuse storing circuit. The selecting circuit...
US-9,613,713 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes: first and second memory cells; first and second word lines coupled to the first and second...
US-9,613,712 Negative voltage management module for an address decoder circuit of a non-volatile memory device
An address decoder circuit is designed to address and bias memory cells of a memory array of a non-volatile memory device. The address decoder circuit includes...
US-9,613,711 Storage device and method of reading a storage device in which reliability verification operation is...
A method controlling the execution of a reliability verification operation in a storage device including a nonvolatile memory device includes; determining...
US-9,613,710 Multiple-time programmable memory
A multiple-time programmable (MTP) structure is provided that can operate using a power supply with a supply voltage of 1.5 V to 5.5 V. When the supply voltage...
US-9,613,709 Dual non-volatile memory cell comprising an erase transistor
The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating...
US-9,613,708 Data storage device and data maintenance method
A data storage device including a flash memory and a controller. The flash memory includes a plurality of pages and a plurality of word lines, wherein each of...
US-9,613,707 Data programming method for avoiding unavailability of rewritable non-volatile memory module due to higher...
A data programming method includes setting a plurality of first type physical erasing units as a current writing area and recording a current writing data...
US-9,613,706 Programming and/or erasing a memory device in response to its program and/or erase history
A method includes sending a number of program/erase cycles from a memory of control logic of a memory device to a counter of the control logic, where the number...
US-9,613,705 Method for managing programming mode of rewritable non-volatile memory module, and memory storage device and...
In an exemplary embodiment, the method includes: determining whether a used capacity of first physical units initially configured to be programmed based on a...
US-9,613,704 2D/3D NAND memory array with bit-line hierarchical structure for multi-page concurrent SLC/MLC program and...
This invention discloses 2D or 3D NAND flash array in two-level BL-hierarchical structure with flexible multi-page or random-page-based concurrent, mixed SLC...
US-9,613,703 Semiconductor memory device
A semiconductor memory device for high speed operation, and for flexible data reading and programming is disclosed. The flash memory of the present disclosure...
US-9,613,702 NAND flash memory device with oblique architecture and memory cell array
A memory device including multiple word lines, multiple bit lines and a memory cell array is provided. The word lines intersect the bit lines, and an included...
US-9,613,701 Ternary content addressable memory (TCAM) with programmable resistive elements
A content addressable memory device includes a first memory cell having three programmable resistive elements coupled in parallel. The first terminals of the...
US-9,613,700 TCAM field enable logic
A content addressable memory ("CAM") field enabling logic comprises fields and field enable logics. The fields each have local match lines and a corresponding...
US-9,613,699 Memory system with a content addressable superconducting memory
A memory system including a content addressable memory having an array of content addressable memory elements including a plurality of rows of content...
US-9,613,698 Set and reset operation in phase change memory and associated techniques and configurations
Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In an...
US-9,613,697 Resistive memory device
A resistive memory device includes a memory cell array having a plurality of memory cells respectively connected to a plurality of first signal lines and a...
US-9,613,696 Memory device including decoder for a program pulse and related methods
An integrated circuit includes an array of phase-change memory (PCM) cells, and bitlines coupled to the array of PCM cells. The integrated circuit also includes...
US-9,613,695 Methods, devices and systems using over-reset state in a memory cell
Memory cells, devices and methods are disclosed, including those that involve applying a waveform to a resistive memory cell to program the memory cell to an...
US-9,613,694 Enhanced programming of two-terminal memory
Two-terminal memory can be set to a first state (e.g., conductive state) in response to a program pulse, or set a second state (e.g., resistive state) in...
US-9,613,693 Methods for setting a resistance of programmable resistance memory cells and devices including the same
A method can include applying a first electric field to a plurality of memory elements that are programmable between at least two different resistance states;...
US-9,613,692 Sense amplifier for non-volatile memory devices and related methods
A memory device includes an array of phase-change memory (PCM) cells and complementary PCM cells. A column decoder is coupled to the array of PCM cells and...
US-9,613,691 Apparatus and method for drift cancellation in a memory
An apparatus is provided which comprises: a plurality of memory cells; a bias logic coupled with at least one memory cell of the plurality, the bias logic to:...
US-9,613,690 Resistive memory device and operation method thereof
A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell...
US-9,613,689 Self-selecting local bit line for a three-dimensional memory array
A three-dimensional memory device includes an alternating stack of word lines and insulating layers, a plurality of gate lines, a plurality of global bit lines,...
US-9,613,687 Memory, memory controller, memory system, method of memory, memory controller and memory system
In one embodiment, the method includes performing a read operation on a memory, and determining, by a memory controller, whether to perform a reliability...
US-9,613,686 Management of data storage in memory cells using a non-integer number of bits per cell
A method for data storage includes storing data in a group of memory cells, by encoding the data using at least an outer code and an inner code, and optionally...
US-9,613,685 Burst mode read controllable SRAM
A static random access memory (SRAM) includes an array of storage cells arranged as rows and columns and a read controller to manage reading from the storage...
US-9,613,684 Systems and methods involving propagating read and write address and data through multi-bank memory circuitry
Multi-bank SRAM devices, systems, methods of operating multi-bank SRAMs, and/or methods of fabricating multi-bank SRAM systems are disclosed. For example,...
US-9,613,682 FinFET 6T SRAM cell structure
A static memory circuit includes a pull-up transistor, a pull-down transistor, a pass-gate transistor associated with the pull-up and pull-down transistors, and...
US-9,613,681 Voltage generation circuit
A voltage generation circuit may include: a main code table suitable for outputting a main code based on an operation signal; a main voltage generator suitable...
US-9,613,680 Semiconductor device with improved sense margin of sense amplifier
Semiconductor devices capable of a sensing margin of a semiconductor device are described. A semiconductor device may include a plurality of mats, a plurality...
US-9,613,679 Controlled dynamic de-alignment of clocks
A controller includes first and second functional units, first and second clock-signal sources that provide corresponding first and second clock signals that...
US-9,613,678 Semiconductor apparatus including multichip package
A semiconductor apparatus including a multichip package is disclosed. The semiconductor apparatus includes a slave chip having a slave region and a master...
US-9,613,677 Semiconductor devices and semiconductor systems including the same
A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs an external command and...
US-9,613,676 Writing to cross-point non-volatile memory
Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a...
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