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Patent # Description
US-9,647,682 Data compression system and method
A divider divides an input data into a plurality of data blocks. A hash calculator calculates a hash value of each data block. A compression dictionary memory...
US-9,647,680 Walsh encoding for peripheral sensor interface 5
A sensor may encode data using a first encoding scheme. The first encoding scheme may include encoding a data bit, included in the data, using a first chip...
US-9,647,679 Methods and apparatus for a delta sigma ADC with parallel-connected integrators
Various embodiments of the present technology may comprise a method and device for a delta-sigma ADC. The method and device may comprise receiving an input...
US-9,647,678 Method for operating radio frequency digital to analog conversion circuitry in the event of a first and a...
A method for operating a radio frequency digital to analog conversion circuitry with a number of cells if a first input sample and a subsequent second input...
US-9,647,677 Integrator, AD converter, and radiation detection device
An integrator according to an embodiment includes first and second nodes, first to fifth switches, first and second main integration capacitors, and a first...
US-9,647,676 Method and apparatus for reducing SAR input loading
The disclosure provides a successive approximation register analog to digital converter (SAR ADC). The SAR ADC includes a charge sharing DAC that includes an...
US-9,647,674 Apparatus for generating clock signals having a PLL part and synthesizer part with programmable output dividers
A clock signal generator responsive to synchronization pulses to perform actions has a phase locked loop (PLL) part including a digitally controlled oscillator...
US-9,647,673 Controllable circuits, processes and systems for functional ESD tolerance
An electronic circuit (100) includes a first circuit (140) having an output and operable to give a warning but that has a sensitivity to an electrostatic...
US-9,647,672 Digitally compensated phase locked oscillator
A digitally compensated phase locked oscillator (DCPLO) is disclosed herein. The DCPLO comprises: a DCPLO input for receiving a reference signal at a known...
US-9,647,671 High performance phase frequency detectors
A phase frequency detector with two stages of operation; each stage containing two D flip-flops. Each D flip-flop is interconnected to eliminate detection dead...
US-9,647,670 Oscillator with dynamic gain control
In one form, an oscillator includes an oscillator core circuit and a dynamic gain control circuit. The oscillator core circuit is for connection to a frequency...
US-9,647,668 Apparatus for flexible electronic interfaces and associated methods
A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer...
US-9,647,667 Hybrid architecture for signal processing and signal processing accelerator
Systems and methods for configuring circuitry for use with a field programmable gate array (FPGA) are disclosed. The circuitry includes an array of signal...
US-9,647,666 Transmitter and semiconductor device
A transmitter may include a pre-driver and a main driver. The pre-driver may be configured to generate a pull-up signal and a pull-down signal in response to an...
US-9,647,665 Semiconductor device and electronic device
To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. A semiconductor...
US-9,647,664 Output driver, semiconductor apparatus, system, and computing system using the same
A semiconductor apparatus may include an output driver configured to output an internal signal to an external device. The output driver may include a pad...
US-9,647,663 Differential input buffer circuits and methods
An input buffer circuit that receives differential signals includes a first resistive path circuit, a second resistive path circuit and a feedback circuit. The...
US-9,647,662 Superconducting tunable coupler
A superconducting system is provided that includes a coplanar superconducting circuit. The coplanar superconducting circuit includes a first ground plane...
US-9,647,661 Temperature compensation circuit, temperature compensation method and liquid crystal display
Disclosed are a temperature compensation circuit for a display panel, a temperature compensation method and a liquid crystal display. The temperature...
US-9,647,660 Apparatus and method for universal high range level shifting
Apparatus for converting a first input signal from a first voltage domain to an output signal for a second voltage domain, the apparatus configured to operate...
US-9,647,659 Semiconductor devices
A semiconductor device with impedance calibration includes a first channel circuit of a first channel and a second channel circuit of a second channel. The...
US-9,647,658 Resistive interpolation for a touch sensor with opaque conductive material
In one embodiment, an apparatus comprises a substrate. The apparatus further comprises a plurality of drive electrodes disposed on the substrate. Each of the...
US-9,647,657 Programmable slew rate power path switch with integrated super capacitor charging system
A fully integrated circuit configuration that can be used to control the power path of a pair of PMOS load switches is described. The circuit also integrates a...
US-9,647,656 Integrated circuit and transmission and reception apparatus
An integrated circuit includes a transistor, and an impedance matching circuit coupled with the transistor. The impedance matching circuit includes a signal...
US-9,647,655 Current to frequency converter
According to one aspect, embodiments herein provide a current to frequency converter comprising a node configured to be coupled to a photodetector and to...
US-9,647,654 Monitor circuit, semiconductor integrated circuit, semiconductor device, and method of controlling power supply...
A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a...
US-9,647,653 Method for reduced power clock frequency monitoring
An apparatus may include first and second clock monitors. The first clock monitor may be configured to receive a first clock signal and assert a first signal if...
US-9,647,651 Delay circuit and semiconductor device
To provide a delay circuit improved in the accuracy of a delay time. A delay circuit is provided which includes a plurality of switches respectively provided...
US-9,647,650 Clock generating device
A clock generating device includes a first timing delay module, a multiplexer, and a second timing delay module. The multiplexer is electrically connected to...
US-9,647,649 Method and system for cancellation of spurious signals
Systems and methods for generating a spurious signal cancellation signal, the system comprising two direct digital synthesizers (DDS). The first DDS provides...
US-9,647,648 Signal processor
A signal processor includes an amplifier that amplifies a control signal which is input into the amplifier to output an amplified control signal; and a...
US-9,647,647 Semiconductor device
A semiconductor device includes a first circuit block that is connected between a first power supply voltage line and a first reference voltage line, a second...
US-9,647,646 Systems and methods for gain and offset control
A method for setting an initial gain and an initial offset for an automatic gain and offset controller (AGOC) is described. The method includes determining a...
US-9,647,645 Low voltage to high voltage level translator that is independent of the high supply voltage
A low voltage to high voltage level translator that is independent of the high supply voltage. The translator includes first and second transistors with current...
US-9,647,644 Low-power, small-area, high-speed master-slave flip-flop circuits and devices including same
An integrated circuit includes a plurality of positive edge-triggered master-slave flip-flop circuits sharing a clock signal. At least one of the positive...
US-9,647,643 Low power buffer with gain boost
The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of...
US-9,647,642 Clock phase adjustment mechanism of a ring oscillator using a phase control signal
A clock generator comprises a voltage controlled oscillator including a ring oscillator which has a plurality of differential inverter circuits connected in a...
US-9,647,641 Weakly coupled tunable RF receiver architecture
RF communications circuitry, which includes a first tunable RF filter and a first RF low noise amplifier (LNA) is disclosed. The first tunable RF filter...
US-9,647,640 Semi-analog FIR filter with high impedance state
A system and method is disclosed for placing some of the elements of a FIR filter into a high impedance state in certain situations. When it is detected that...
US-9,647,639 Baseband filters and interfaces between a digital-to-analog converter and a baseband filter
Exemplary embodiments of the present disclosure are related to baseband filters. A device may include a digital-to-analog converter (DAC) configured to output a...
US-9,647,638 Architecture to reject near end blockers and transmit leakage
A method and apparatus for minimizing transmit signal interference is provided. The method includes the steps of: receiving a signal and amplifying the received...
US-9,647,637 Saw filter with improved stop band suppression
A filter working with surface acoustic waves comprises a piezoelectric substrate (SU), a first transducer (IDT1) arranged in the acoustic track coupled to an...
US-9,647,636 Piezoelectric package-integrated delay lines for radio frequency identification tags
Embodiments of the invention include delay line circuitry that is integrated with an organic substrate. Organic dielectric material and a plurality of...
US-9,647,635 Elastic wave resonators, and elastic wave filters, antenna duplexers, modules and communication devices using same
An elastic wave resonator including comb-shaped electrodes and reflector electrodes formed on a piezoelectric substrate. In one example, an overlapping portion...
US-9,647,634 Elastic wave filter device and duplexer comprising magnetically coupled inductances
In an elastic wave filter device, a package substrate is provided with an elastic wave filter chip defining a ladder circuit including a plurality of series arm...
US-9,647,633 Acoustic wave element, branching filter and communication module
SAW element has a substrate; an IDT having a first comb-shaped electrode and a second comb-shaped electrode located on an upper surface of the substrate; and a...
US-9,647,632 Lumped element radio frequency tuning calibration process
A preferred method for efficiently tuning RF ports while avoiding conventional labor intensive, step-by-step processes is disclosed. The method may use at least...
US-9,647,630 Antenna impedance matching apparatus, semiconductor chip, and method
The present invention provides an antenna impedance matching apparatus, semiconductor chip, and method. The apparatus includes: a semiconductor chip, including...
US-9,647,629 Variable capacitors for high accuracy tuning
Improved interdigital parallel plate rotary capacitors to be used in automatic MHz range tuners have a grounding technique based on bronze sliding contact to...
US-9,647,628 Low-loss tunable radio frequency filter
A method of constructing an RF filter comprises designing an RF filter that includes a plurality of resonant elements disposed, a plurality of non-resonant...
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