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Patent # Description
US-9,647,112 Fabrication of strained vertical P-type field effect transistors by bottom condensation
A method of forming a strained vertical p-type field effect transistor, including forming a counter-doped layer at a surface of a substrate, forming a...
US-9,647,111 Advanced forming method and structure of local mechanical strained transistor
Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer...
US-9,647,110 Layout for LDMOS
A layout structure, a semiconductor device and an electronic apparatus are provided. The layout structure includes at least one LDMOS. The LDMOS includes a...
US-9,647,109 Semiconductor device
According to one embodiment, the fifth semiconductor region contacts the first semiconductor region. The metal region is provided on the fifth semiconductor...
US-9,647,108 Silicon carbide semiconductor device
A silicon carbide semiconductor device includes: a substrate; a drift layer; a current dispersion layer; a base region; a source region; trenches; a gate...
US-9,647,106 Silicon carbide semiconductor device and method for manufacturing same
A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, a gate electrode, an interlayer insulating film, and a gate...
US-9,647,105 Semiconductor device and method of manufacturing the same
A semiconductor device includes: a substrate; nitride semiconductor layers disposed over the substrate; a source electrode and a drain electrode disposed over...
US-9,647,104 Group III-nitride-based enhancement mode transistor having a heterojunction fin structure
A Group III-nitride-based enhancement mode transistor having a heterojunction fin structure and a corresponding semiconductor device are described.
US-9,647,103 Semiconductor device with modulated field element isolated from gate electrode
The current invention introduces a modulated field element incorporated into the semiconductor device outside the controlling electrode and active areas. This...
US-9,647,102 Field effect transistor
A field effect transistor includes a substrate; a first semiconductor layer, disposed over the substrate; a second semiconductor layer, disposed over the first...
US-9,647,101 Silicene material layer and electronic device having the same
Provided are silicene material layers and electronic devices having a silicene material layer. The silicene material layer contains silicon atoms in a...
US-9,647,100 Semiconductor device with auxiliary structure including deep level dopants
A semiconductor device includes transistor cells formed along a first surface at a front side of a semiconductor body in a transistor cell area. A drift zone...
US-9,647,099 Semiconductor-on-insulator (SOI) lateral heterojunction bipolar transistor having an epitaxially grown base
A method of forming a semiconductor structure includes providing an emitter and a collector on a surface of an insulator layer. The emitter and the collector...
US-9,647,098 Thermionically-overdriven tunnel FETs and methods of fabricating the same
A field effect transistor (FET) includes a nanosheet stack having first and second stacked semiconductor channel layers. The first channel layer defines a...
US-9,647,097 Vertical tunnel field effect transistor (FET)
Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein....
US-9,647,095 Semiconductor device and method for manufacturing the same
A semiconductor device formed using an oxide semiconductor layer and having small electrical characteristic variation is provided. A highly reliable...
US-9,647,094 Method of manufacturing a semiconductor heteroepitaxy structure
A method of manufacturing a semiconductor structure includes the steps of depositing a layer of semiconductor oxide on a base semiconductor layer, scavenging...
US-9,647,093 Fin cut for taper device
A method of making a semiconductor device includes patterning a fin in a substrate; performing a first etching process to remove a portion of the fin to cut the...
US-9,647,092 Method and structure of forming FinFET electrical fuse structure
An e-Fuse structure is provided on a surface of an insulator layer of a semiconductor-on-insulator substrate (SOI). The e-Fuse structure includes a first metal...
US-9,647,091 Annealed metal source drain overlapping the gate
A method of forming a field effect transistor is provided. The method of forming a field effect transistor may include forming a dummy gate perpendicular to and...
US-9,647,090 Surface passivation for germanium-based semiconductor structure
The present disclosure provides a method forming a semiconductor device in accordance with some embodiments. The method includes receiving a substrate having a...
US-9,647,089 Thin film transistor substrate, display apparatus including the same, method of manufacturing thin film...
Thin film transistor substrate includes: a substrate; a crystalline silicon layer on the substrate; and a capping layer covering the crystalline silicon layer...
US-9,647,088 Manufacturing method of low temperature polysilicon thin film transistor
The invention provides a manufacturing method of a low temperature polysilicon thin film transistor, including: providing a substrate; forming a buffer layer on...
US-9,647,087 Doped protection layer for contact formation
A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with a gate stack formed on the semiconductor...
US-9,647,086 Early PTS with buffer for channel doping control
A method of performing an early PTS implant and forming a buffer layer under a bulk or fin channel to control doping in the channel and the resulting bulk or...
US-9,647,085 CMOS device with double-sided terminals and method of making the same
A transistor device includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a gate structure disposed on the...
US-9,647,084 Semiconductor device and method of manufacturing the same
A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the...
US-9,647,083 Producing a semiconductor device by epitaxial growth
A method of producing a semiconductor device is presented. The method comprises: providing a semiconductor substrate having a surface; epitaxially growing,...
US-9,647,082 Diodes with multiple junctions
A diode includes a semiconductor substrate having a surface; a first contact region disposed at the surface of the semiconductor substrate and having a first...
US-9,647,081 Method for manufacturing silicon carbide semiconductor device
A method for manufacturing a silicon carbide semiconductor device includes steps of preparing a silicon carbide substrate having a first main surface and a...
US-9,647,080 Schottky device and method of manufacture
A Schottky device includes a barrier height adjustment layer in a portion of a semiconductor material. In accordance with an embodiment, the Schottky device is...
US-9,647,079 Thin film transistor array panel and manufacturing method thereof
Disclosed herein is a thin film transistor array panel, including: an insulating substrate; a gate electrode formed on the insulating substrate; a gate...
US-9,647,078 Closed cell configuration to increase channel density for sub-micron planar semiconductor power device
A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region...
US-9,647,077 Power semiconductor devices having a semi-insulating field plate
A power semiconductor device comprising a first metal electrode and a second metal electrode formed on a first substrate surface of a semiconductor substrate, a...
US-9,647,076 Circuit including semiconductor device with multiple individually biased space-charge control electrodes
A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located...
US-9,647,075 Segmented field plate structure
A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer...
US-9,647,074 Semiconductor-substrate manufacturing method and semiconductor-device manufacturing method in which germanium...
A method of manufacturing a semiconductor substrate includes: heat-treating a germanium layer 30 with an oxygen concentration of 1.times.10.sup.16 cm.sup.-3 or...
US-9,647,073 Transistor structures and fabrication methods thereof
Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially...
US-9,647,072 Silicon carbide semiconductor device
A silicon carbide semiconductor device has a silicon carbide substrate, a gate insulating film, and a gate electrode. Silicon carbide substrate includes a first...
US-9,647,071 FINFET structures and methods of forming the same
FinFETs and methods of forming finFETs are described. According to some embodiments, a structure includes a channel region, first and second source/drain...
US-9,647,070 Semiconductor devices with graded dopant regions
Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By...
US-9,647,068 Semiconductor device and manufacturing method thereof
A semiconductor device includes a base dielectric layer, a semiconductor substrate layer disposed on the base dielectric layer, and a transistor disposed in the...
US-9,647,067 FinFET and fabrication method thereof
Present embodiments provide for a FinFET and fabrication method thereof. The fabrication method includes two selective etching processes to form the channel....
US-9,647,066 Dummy FinFET structure and method of making same
A FinFET device may include a dummy FinFET structure laterally adjacent an active FinFET structure to reduce stress imbalance and the effects of stress...
US-9,647,065 Bipolar transistor structure having split collector region and method of making the same
A bipolar transistor includes a substrate and a first well in the substrate, the first well having a first dopant type. The bipolar transistor further includes...
US-9,647,064 Semiconductor device and related electronic device
A semiconductor device may include the following elements: a first n-type region; a second n-type region; a p-type region, which directly contacts each of the...
US-9,647,063 Nanoscale chemical templating with oxygen reactive materials
A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided....
US-9,647,062 Silicon nanowire formation in replacement metal gate process
Techniques for a semiconductor device are provided. Techniques are directed to forming a semiconductor device by: forming a fin structure in a substrate,...
US-9,647,061 Electronic device of vertical MOS type with termination trenches having variable depth
An electronic device is integrated on a chip of semiconductor material having a main surface and a substrate region with a first type of conductivity. The...
US-9,647,060 Isolation structure and method for fabricating the same
A method for fabricating isolation device is disclosed. The method includes the steps of: providing a substrate; forming a shallow trench isolation (STI) in the...
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