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Patent # Description
US-9,647,006 Light shielding pattern pixel structure having a one side overlapping scan line
An active device of a pixel structure includes a semiconductor layer, an insulation layer covering the semiconductor layer, a gate electrode disposed on the...
US-9,647,005 Display device and manufacturing method thereof
A display device includes: a gate electrode, a gate line, and data lines on a substrate, the data lines in a same layer as the gate line; a gate insulating...
US-9,647,004 Display
A display is disclosed. The display includes a display panel including pixel units in an image-displaying region. Each of the pixel units includes an AND gate...
US-9,647,003 Display device
A display device includes a display panel including gate lines and data lines, the gate lines and the data lines intersecting, and pixels defined at the...
US-9,647,002 Array substrate, manufacture method thereof, and display device with the array substrate
An array substrate, a manufacture method thereof, and a display device with the array substrate are provided. The array substrate includes a substrate; a first...
US-9,647,001 Array substrate, method for fabricating the same and display device
An array substrate, a method for fabricating the same and a display device are disclosed. The array substrate includes a base substrate, and further includes a...
US-9,647,000 Display device
A display device includes a first electrode, a first insulating layer having a first top surface and a first side wall, the first side wall having a closed...
US-9,646,999 Thin film transistor, array substrate and method of forming the same
The present disclosure proposes a TFT. The source and the drain of the TFT are disposed on the same side as the gate. The gate includes a first buffer layer, a...
US-9,646,998 Array substrate and manufacturing method thereof, as well as display device
This disclosure provides an array substrate and manufacturing method thereof, as well as a display device, the array substrate comprising: a substrate and a...
US-9,646,997 Array substrate, method for manufacturing the same and display device
The present invention provides an array substrate. The active layer of the array substrate comprises at least two metal oxide semiconductor layers, wherein the...
US-9,646,995 FFS array substrate and liquid crystal display device having the same
An FFS array substrate and a liquid crystal display device having the same are disclosed. The FFS array substrate includes a substrate, first metal layer, a...
US-9,646,994 Semiconductor devices and manufacturing methods thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first fin field effect transistor...
US-9,646,993 Single-chip field effect transistor (FET) switch with silicon germanium (SiGe) power amplifier and methods of...
Various embodiments include field effect transistors (FETs) and related integrated circuit (IC) layouts. One FET includes: a silicon substrate including a set...
US-9,646,992 Semiconductor memory
According to one embodiment, a semiconductor memory 100 includes a memory cell array 100A composed of a plurality of SRAM cells 10 including NMOS transistors...
US-9,646,991 Semiconductor device with surrounding gate transistors in a NOR circuit
A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NOR circuit. The NOR circuit is formed by...
US-9,646,990 NAND memory strings and methods of fabrication thereof
Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different...
US-9,646,989 Three-dimensional memory device
According to one embodiment, the plurality of contact vias extend in the stacking direction in the insulating layer, and are in contact with the end parts of...
US-9,646,988 Semiconductor memory device and method for manufacturing same
According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate, the stacked body including a...
US-9,646,987 Semiconductor memory device and production method thereof
A semiconductor memory device according to an embodiment comprises a memory cell array including a stacked body and a semiconductor film, the stacked body...
US-9,646,986 Semiconductor memory device and method of fabricating the same
A semiconductor memory device includes insulating patterns and conductive patterns stacked alternately with each other, penetrating structures passing through...
US-9,646,985 Three-dimensional non-volatile memory device, memory system and method of manufacturing the same
A three-dimensional (3-D) non-volatile memory device includes channel structures each including channel layers stacked over a substrate and extending in a first...
US-9,646,984 Non-volatile memory device
A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly...
US-9,646,983 Semiconductor device and method of manufacturing the same
A semiconductor device includes a plurality of line patterns including at least two continuous line repetition units having, as one of the line repetition unit,...
US-9,646,982 Semiconductor device and method of manufacturing the semiconductor device
According to an embodiment, a manufacturing method of a semiconductor device includes forming, on a film to be processed, a plurality of first core material...
US-9,646,981 Passive devices for integration with three-dimensional memory devices
A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing...
US-9,646,980 Logic compatible flash memory cells
A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a...
US-9,646,979 Non-volatile semiconductor storage device
To propose a non-volatile semiconductor memory device capable of injecting charge into a floating gate by source side injection even in a single-layer gate...
US-9,646,978 Self-aligned flash memory device with word line having reduced height at outer edge opposite to gate stack
The present disclosure relates to a flash memory device, and associated methods. In some embodiments, the flash memory device has a gate stack with a control...
US-9,646,977 Nonvolatile memory device and method for fabricating the same
A nonvolatile memory device includes a floating gate formed over a substrate; a contact plug formed on a first side of the floating gate and disposed parallel...
US-9,646,976 Ferroelectric random-access memory with pre-patterned oxygen barrier
Structure of F-RAM cells are described. The F-RAM cell include a contact extending through a first dielectric layer on a surface of a substrate. A barrier...
US-9,646,975 Lateral stack of cobalt and a cobalt-semiconductor alloy for control gate electrodes in a memory structure
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures and a backside trench are formed...
US-9,646,974 Dual-port static random access memory
A dual-port static random access memory (SRAM) cell includes first through third power lines, a storage unit connected to the first through third power lines, a...
US-9,646,973 Dual-port SRAM cell structure with vertical devices
Dual-Port SRAM cells are described. In an embodiment, a cell includes first and second pull-down, first and second pull-up, and first through fourth pass-gate...
US-9,646,971 Semiconductor devices including nanowire capacitors and fabricating methods thereof
Semiconductor devices and fabricating methods thereof are provided. A semiconductor device may include a substrate, a metal layer on the substrate, a seed layer...
US-9,646,970 Floating body memory cell having gates favoring different conductivity type regions
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is...
US-9,646,969 Spacer chamfering gate stack scheme
A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are...
US-9,646,967 Semiconductor device
Semiconductor devices are provided. The semiconductor device includes a first fin portion and a second fin portion arranged on a substrate and extended in a...
US-9,646,966 N-channel and P-channel end-to-end finFET cell architecture
A finFET block architecture uses end-to-end finFET blocks. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor...
US-9,646,965 Monolithically integrated transistors for a buck converter using source down MOSFET
An integrated semiconductor transistor chip for use in a buck converter includes a high side transistor formed on the chip and comprising a laterally diffused...
US-9,646,964 Semiconductor device
The invention provides a semiconductor device. The semiconductor device includes a buried oxide layer disposed on a substrate. A semiconductor layer having a...
US-9,646,963 Integrated circuits with capacitors and methods for producing the same
Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate with an active layer...
US-9,646,962 Low leakage gate controlled vertical electrostatic discharge protection device integration with a planar FinFET
A semiconductor device includes an electrostatic discharge (ESD) device formed adjacent to a first fin field effect transistor (finFET). The device includes a...
US-9,646,961 Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including...
An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells...
US-9,646,960 System-on-chip devices and methods of designing a layout therefor
A system-on-chip device may include a substrate with an active pattern, a gate electrode crossing the active pattern and extending in a first direction, and a...
US-9,646,959 Slim bezel and display having the same
A bezel of a display includes source lines with a same length, gate in panel (GIP) lines, and at least two customized integrated circuit (IC) chips arranged...
US-9,646,958 Integrated circuits including dummy structures and methods of forming the same
An integrated circuit includes a core area. The core area has at least one edge region and a plurality of transistors disposed in the edge region. A plurality...
US-9,646,956 Light emitting device package
Embodiments provide a light emitting device package including a package body having a top-opened cavity disposed in at least a portion thereof, a first...
US-9,646,955 Packages and methods of forming packages
Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated...
US-9,646,954 Integrated circuit with test circuit
An integrated circuit system comprising a first integrated and at least one of a second integrated circuit, interposer or printed circuit board. The first...
US-9,646,953 Integrated circuit packaging techniques and configurations for small form-factor or wearable devices
Embodiments of the present disclosure are directed toward integrated circuit (IC) packaging techniques and configurations for small form-factor or wearable...
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