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Patent # Description
US-9,646,952 Microelectronic package debug access ports
A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment,...
US-9,646,951 Method of forming a semiconductor device and structure therefor
In one embodiment, a conductor bump is formed on an under bump conductor of a semiconductor device to extend a first distance away from a surface of the under...
US-9,646,950 Corrosion-resistant copper bonds to aluminum
A method for fabricating a semiconductor device is disclosed. A packaged semiconductor device is provided having copper ball bonds attached to aluminum pads....
US-9,646,949 Solderless mounting for semiconductor lasers
A first contact surface of a semiconductor laser chip can be formed to a first target surface roughness and a second contact surface of a carrier mounting can...
US-9,646,948 Electronic component and method for manufacturing electronic component
An electronic component comprises: a resin frame; a semiconductor substrate housed in the resin frame; a plate shape metal member having at least one end fixed...
US-9,646,947 Integrated circuit with inductive bond wires
An integrated circuit (IC) that includes a semiconductor die in an IC package. The semiconductor die includes an electrical endpoint. The IC also includes a pad...
US-9,646,946 Fan-out wafer-level packaging using metal foil lamination
Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to...
US-9,646,945 Semiconductor device having solder joint and method of forming the same
Provided is a semiconductor device having a high-reliability solder joint. The semiconductor device includes a high-temperature solder formed on a conductive...
US-9,646,944 Alignment structures and methods of forming same
Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is a method of forming an...
US-9,646,943 Connector structure and method of forming same
Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first...
US-9,646,942 Mechanisms for controlling bump height variation
The mechanisms for forming bumps on packaged dies and package substrates reduce variation of bump heights across the packaged dies and packaged substrates....
US-9,646,941 Semiconductor packaging device including via-in pad (VIP) and manufacturing method thereof
A semiconductor device includes a carrier and a metallic structure including a metallic member, a pad and a via portion; wherein the metallic member is disposed...
US-9,646,940 Gas barrier film and electronic device
The gas barrier film including, on a base, a first gas barrier layer which is formed by a physical vapor deposition method or a chemical vapor deposition method...
US-9,646,939 Multilayer structure in an integrated circuit for damage prevention and detection and methods of creating the same
Various embodiments facilitate die protection for an integrated circuit. In one embodiment, a multilayer structure is formed in multiple levels and along the...
US-9,646,938 Integrated circuit with backside structures to reduce substrate warp
Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include...
US-9,646,937 Packaging structure for thin die and method for manufacturing the same
A packaging structure for thin die is provided. The packaging structure has a substrate, a thin die, a strengthening layer and an encapsulation body. The thin...
US-9,646,936 Intramodule radio frequency isolation
A radio frequency (RF) module comprises RF-shielding structure for providing three-dimensional electromagnetic interference shielding with respect to one or...
US-9,646,935 Heat sink of a metallic shielding structure
A heat sink of a metallic shielding structure is provided in this disclosure, which includes a heating module and a cooling module. The heating module includes...
US-9,646,934 Integrated circuits with overlay marks and methods of manufacturing the same
Integrated circuits and methods for manufacturing the same are provided. An integrated circuit includes a base dielectric layer, a first dielectric layer...
US-9,646,933 Semiconductor device and manufacturing method thereof
According to one embodiment, a semiconductor device includes a first insulating layer on an underlying layer, a first trench formed in the first insulating...
US-9,646,932 Method for forming interconnect structure that avoids via recess
A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is...
US-9,646,931 Formation of liner and metal conductor
In one aspect of the invention, a method for fabricating an advanced metal conductor structure includes a conductive line pattern including a set of conductive...
US-9,646,930 Semiconductor device having through-substrate vias
A semiconductor device having through-substrate vias is disclosed. In one aspect, the device includes a substrate having at least one front-end-of-line (FEOL)...
US-9,646,929 Making an efuse
A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second...
US-9,646,928 Semiconductor arrangement and formation thereof
A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal trace under at least a first dielectric layer...
US-9,646,927 Power semiconductor device
A power semiconductor device includes a first polarity-side semiconductor element whose first principal electrode is in contact with a first polarity-side...
US-9,646,926 Wiring substrate and method of manufacturing the same
A wiring substrate includes a first wiring layer including a first wiring part having a first wiring interval and a second wiring part having a second wiring...
US-9,646,925 Interconnect array pattern with a 3:1 signal-to-ground ratio
An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of...
US-9,646,924 Interposer, method for manufacturing interposer, and semiconductor device
Electrodes pads formed on device surfaces connect semiconductor chips to through electrodes of an intermediate substrate. A flow path is formed inside the...
US-9,646,923 Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices
Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a semiconductor device includes a...
US-9,646,922 Methods and apparatus for thinner package on package structures
Methods and apparatus for thinner package on package ("PoP") structures. A structure includes a first integrated circuit package including at least one...
US-9,646,921 Semiconductor package and fabrication method thereof
A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second...
US-9,646,920 Power semiconductor device with small contact footprint and the preparation method
A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and a...
US-9,646,919 Semiconductor package for a lateral device and related methods
A semiconductor package. Implementations may include a lateral device that may include a lateral semiconductor device including one of interspersed and...
US-9,646,918 Semiconductor device and method
A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent...
US-9,646,917 Low CTE component with wire bond interconnects
A component such as an interposer or microelectronic element can be fabricated with a set of vertically extending interconnects of wire bond structure. Such...
US-9,646,916 Method and apparatus to facilitate direct surface cooling of a chip within a 3D stack of chips using optical...
In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very...
US-9,646,915 Heat dissipation device and semiconductor device
In a laminating direction of first to fifth ceramic sheets, a first slit and a second slit are positioned closer to a first mounting section and a second...
US-9,646,914 Process for producing a microfluidic circuit within a three-dimensional integrated structure, and corresponding...
A three-dimensional integrated structure includes a first and a second element each having an interconnection part formed by metallization levels encased in an...
US-9,646,913 Thermal interface material on package
A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes...
US-9,646,912 Semiconductor device and semiconductor module having cooling fins
A semiconductor module having a plurality of cooling fins and a fixing cooling fin longer than the plurality of cooling fins, the fixing cooling fin having a...
US-9,646,911 Composite substrate
A composite substrate configured for epitaxial growth of a semiconductor layer thereon is provided. The composite substrate includes multiple substrate layers...
US-9,646,910 Integrated heat spreader that maximizes heat transfer from a multi-chip package
In at least some embodiments, an electronic package to maximize heat transfer comprises a plurality of components on a substrate. A stiffener plate is installed...
US-9,646,909 Electrical switch and mounting assembly therefor
A mounting assembly is for an electrical switch, such as for example, a dimmer switch, which includes a heat sink. The mounting assembly includes a switching...
US-9,646,908 Method for manufacturing semiconductor device and semiconductor device
In a method for manufacturing a semiconductor device, a resin layer including an inorganic filler is molded on a surface of a substrate which includes...
US-9,646,907 Mold package and manufacturing method thereof
A mold package includes a substrate having a first surface and a second surface disposed opposite to the first surface, a wiring part disposed on the first...
US-9,646,906 Semiconductor package with printed sensor
A method forming packaged semiconductor devices includes providing a completed semiconductor package having a die with bond pads coupled to package pins. Sensor...
US-9,646,905 Fingerprint sensor package and method for fabricating the same
The invention provides a fingerprint sensor package and a method for fabricating the same. The fingerprint sensor package includes a substrate. A first...
US-9,646,904 Curable resin composition, and cured product of same
The curable resin composition according to the present invention includes a polyorganosiloxane (A), a silsesquioxane (B), an isocyanurate compound (C), and a...
US-9,646,903 Thermoset polymides for microelectronic applications
Dendrimer/hyperbranched materials are combined with polyimide to form a low CTE material for use as a dielectric substrate layer or an underfill. In the...
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