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Patent # Description
US-9,646,902 Paired edge alignment
Among other things, one or more systems and techniques for scanner alignment sampling are provided. A set of scan region pairs are defined along a periphery of...
US-9,646,901 Semiconductor device with bond pad wiring lead-out arrangement avoiding bond pad probe mark area
Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening...
US-9,646,900 Programmable addressable test chip
A programmable test chip includes a target chip to be tested and addressing circuits fabricated on the same wafer. The addressing circuits can be placed in the...
US-9,646,899 Interconnect assemblies with probed bond pads
An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The...
US-9,646,898 Methods for treating a substrate by optical projection of a correction pattern based on a detected spatial heat...
Techniques herein include systems and methods that provide a spatially-controlled or pixel-based projection of light onto a substrate to tune various substrate...
US-9,646,897 Die crack detector with integrated one-time programmable element
The embodiments described herein provide a die crack detector and method that use a conductive trace arranged to at least substantially extend around a...
US-9,646,896 Lithographic overlay sampling
Some embodiments of the present disclosure relate to a method of alignment which includes defining a plurality of fields on the face of a wafer, and organizing...
US-9,646,895 Semiconductor package and manufacturing method thereof
A method of manufacturing a semiconductor package includes providing a semiconductor chip including a circuit pattern, a connection pad, a first test pad and a...
US-9,646,894 Packaging mechanisms for dies with different sizes of connectors
Embodiments of mechanisms for forming a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical...
US-9,646,893 Method and apparatus for reducing radiation induced change in semiconductor structures
Embodiments of the present disclosure relate to an apparatus and a method for reducing the adverse effects of exposing portions of an integrated circuit (IC)...
US-9,646,892 Transistor device and a method of manufacturing same
A transistor device is provided that includes a substrate, a first channel region formed in a first portion of the substrate and being doped with a dopant of a...
US-9,646,891 Metal-oxide semiconductor field effect transistor, method of fabricating the same, and semiconductor apparatus...
Example embodiments relate to a metal-oxide semiconductor field effect transistor (MOSFET) of a high performance operating with a necessary threshold voltage...
US-9,646,890 Replacement metal gates to enhance transistor strain
Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.
US-9,646,889 Method of removing a hard mask layer on a gate structure while forming a protective layer on the surface of a...
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure on the...
US-9,646,888 Technique of reducing shallow trench isolation loss during fin formation in finFETs
A method of fabricating a semiconductor device includes: providing a semiconductor substrate including a hard mask layer; performing, using the hard mask layer,...
US-9,646,887 Tailored silicon layers for transistor multi-gate control
Disclosed is a process of making field-effect transistor gate stacks containing different deposited thin film silicon material layers having different hydrogen...
US-9,646,885 Method to prevent lateral epitaxial growth in semiconductor devices by performing plasma nitridation process on...
A method for preventing epitaxial growth in a semiconductor device is described. The method cuts the fins of a FinFET structure to form a set of exposed fin...
US-9,646,884 Block level patterning process
The present application relates to an optical planarizing layer etch process. Embodiments include forming fins separated by a dielectric layer; forming a recess...
US-9,646,883 Chemoepitaxy etch trim using a self aligned hard mask for metal line to via
A method of forming metal lines that are aligned to underlying metal features that includes forming a neutral layer atop a hardmask layer that is overlying a...
US-9,646,882 High quality electrical contacts between integrated circuit chips
Methods and structures of connecting at least two integrated circuits in a 3D arrangement by a zigzag conductive chain are disclosed. The zigzag conductive...
US-9,646,881 Hybrid subtractive etch/metal fill process for fabricating interconnects
In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form...
US-9,646,880 Monolithic three dimensional memory arrays formed using sacrificial polysilicon pillars
A method is provided for forming a monolithic three-dimensional memory array. The method includes forming a first vertically-oriented polysilicon pillar above a...
US-9,646,879 Depression filling method and processing apparatus
A depression filling method for filling a depression of a workpiece including a semiconductor substrate and an insulating film formed on the semiconductor...
US-9,646,878 Method for fabricating and manufacturing micro--and nano-fabricated devices and systems securely
A method is disclosed for manufacturing integrated circuits, microelectronics, micro-electro-mechanical systems (MEMS), nano-electro-mechanical systems (NEMS),...
US-9,646,877 Semiconductor device and method of manufacturing the same
A semiconductor device includes an interlayer insulating layer having openings, contact plugs formed in lower parts of the openings, wherein the contact plugs...
US-9,646,876 Aluminum nitride barrier layer
A method of forming features in a dielectric layer is described. A via, trench or a dual-damascene structure may be present in the dielectric layer prior to...
US-9,646,875 Methods of forming memory arrays
Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes...
US-9,646,874 Thermally-isolated silicon-based integrated circuits and related methods
Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material...
US-9,646,873 Method for producing SOS substrates, and SOS substrate
A method for producing SOS substrates which can be incorporated into a semiconductor production line, and is capable of producing SOS substrates which have few...
US-9,646,872 Systems and methods for a semiconductor structure having multiple semiconductor-device layers
A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure...
US-9,646,871 Semiconductor structure with shallow trench isolation and manufacturing method thereof
A semiconductor structure includes a semiconductor substrate and a shallow trench isolation (STI). The STI includes a sidewall interfacing with the...
US-9,646,870 Isolation structures and methods of forming the same
A method of forming a semiconductor structure includes implanting neutral dopants in a first region of a substrate to form a first etching stop feature, the...
US-9,646,869 Semiconductor devices including a diode structure over a conductive strap and methods of forming such...
Semiconductor devices including at least one diode over a conductive strap. The semiconductor device may include at least one conductive strap over an insulator...
US-9,646,868 Wafer temporary bonding method and thin wafer manufacturing method
A method for temporarily bonding a wafer to a support via a temporary bonding arrangement is provided. The arrangement is a composite temporary adhesive layer...
US-9,646,867 Plasma processing apparatus, power supply unit and mounting table system
A plasma processing apparatus includes a mounting table including a lower electrode and an electrostatic chuck, a high frequency power supply electrically...
US-9,646,865 Interconnection structure, fabricating method thereof, and exposure alignment system
In some embodiments, an interconnection structure, an exposure alignment system, and a fabricating method thereof are provided. The method comprises: providing...
US-9,646,864 Substrate processing system and substrate transfer control method
A substrate processing system includes a plurality of processing chambers configured to perform a predetermined processing with respect to substrates, a...
US-9,646,863 Multilayer styrenic resin sheet
Disclosed are a multilayer styrenic resin sheet including 10 to 50 laminated layers which are each made of a styrenic resin composition that includes 29 to 65...
US-9,646,862 Substrate processing apparatus, method of manufacturing semiconductor device and non-transitory...
Heating within a plane of a substrate may be uniform while a thermal budget is decreased. A substrate processing apparatus includes a process chamber configured...
US-9,646,861 Heating plate with heating zones for substrate processing and method of use thereof
A heating plate for use in a substrate support is configured to provide temperature profile control of a substrate supported on the substrate support in a...
US-9,646,860 Alignment systems and wafer bonding systems and methods
Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes...
US-9,646,859 Disk-brush cleaner module with fluid jet
Embodiments of the present invention relates to an apparatus and method for cleaning a substrate using a disk brush. One embodiment provides a substrate cleaner...
US-9,646,858 Semiconductor cleaner systems and methods
In an embodiment, the present invention discloses a EUV cleaner system and process for cleaning a EUV carrier. The euv cleaner system comprises separate dirty...
US-9,646,856 Method of manufacturing a semiconductor device including removing a relief layer from back surface of...
A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad...
US-9,646,855 Semiconductor device with metal carrier and manufacturing method
Semiconductor device including a metal carrier substrate. Above the carrier substrate a first semiconductor layer of Al.sub.x1Ga.sub.y1In.sub.z1N (x1+y1+z1=1,...
US-9,646,854 Embedded circuit patterning feature selective electroless copper plating
Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more...
US-9,646,853 IC device having patterned, non-conductive substrate
A patterned, non-conductive substrate for an integrated circuit (IC) package has a die side configured to receive a die and a lead side opposite the die side. A...
US-9,646,852 Manufacturing process for substrate structure having component-disposing area
A process for a substrate having a component-disposing area is provided, and includes the following steps. A core layer including a first surface, a metallic...
US-9,646,851 Embedded semiconductive chips in reconstituted wafers, and systems containing same
A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are...
US-9,646,850 High-pressure anneal
A method of treating a semiconductor device is provided including the steps of loading the semiconductor device in a processing chamber, pressurizing the...
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