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Patent # Description
US-9,646,698 Semiconductor memory device tunnel insulating layers included in the plurality of memory cells having different...
A semiconductor memory device includes a plurality of memory cells and an X-decoder. The plurality of memory cells are connected to a word line. The X-decoder...
US-9,646,697 Voltage switching circuit and semiconductor apparatus including the same
A voltage switching circuit includes: a control signal generation block configured to include a high voltage switching block which controls an electric current...
US-9,646,696 Semiconductor memory device, erasing methods thereof, and data storage device including the same
A semiconductor device includes a memory block including a plurality of memory cells coupled with a plurality of corresponding word lines, and a peripheral...
US-9,646,695 Content addressable memory and memory cell thereof
A memory cell includes a set of storage switch units, a set of memory units, a set of comparison switch units and a discharge switch unit. The storage switch...
US-9,646,694 10-transistor non-volatile static random-access memory using a single non-volatile memory element and method of...
A memory including an array of nvSRAM cells and method of operating the same are provided. Each nvSRAM cell includes a volatile charge storage circuit, and a...
US-9,646,693 Semiconductor memory having volatile and multi-bit non-volatile functionality and method of operating
A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor...
US-9,646,692 Programming verify for nonvolatile memory
A memory device includes an array of programmable resistance memory cells, a differential amplifier coupled to the array, and current circuitry providing a...
US-9,646,691 Monolithic three dimensional memory arrays with staggered vertical bit lines and dual-gate bit line select...
A monolithic three-dimensional memory array is provided that includes global bit lines disposed above a substrate, each global bit line having a long axis,...
US-9,646,690 Non-volatile memory system with reset verification mechanism and method of operation thereof
A method of operation of a non-volatile memory system includes: providing a resistive storage element having a high resistance state and a low resistance state;...
US-9,646,689 Refresh architecture and algorithm for non-volatile memories
Methods and systems to refresh a nonvolatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device...
US-9,646,688 Three dimensional non-volatile storage with connected word lines
A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied...
US-9,646,687 Resistive memory device and operating method
Provided are a resistive memory device and an operating method for the resistive memory device. The operating method includes detecting a write cycle,...
US-9,646,686 Reconfigurable circuit including row address replacement circuit for replacing defective address
According to one embodiment, a reconfigurable circuit includes circuit blocks arranged with a matrix of A rows and B columns. Each of the circuit blocks...
US-9,646,685 Resistive memory device, resistive memory, and operating method of the resistive memory device
An operating method for a resistive memory device includes; applying a bias control voltage to a memory cell array of the resistive memory device, measuring...
US-9,646,684 PCM memory with margin current addition and related methods
A differential PCM memory may include first and second PCM elements, and a sense amplifier circuit configured to sense a difference between first and second...
US-9,646,683 Memory apparatus, systems, and methods
Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the...
US-9,646,682 Reciprocal quantum logic (RQL) sense amplifier
One embodiment describes a reciprocal quantum logic (RQL) sense amplifier system. The system includes an input stage configured to amplify a sense current...
US-9,646,681 Memory cell with improved write margin
A memory and a method for operating a memory are provided. The memory includes a memory cell having a first circuit to store a bit and a second circuit to...
US-9,646,680 Power gate for latch-up prevention
In an embodiment of the invention, power is provided to an SRAM array without causing latch-up by charging the positive voltage node in the SRAM array and the...
US-9,646,679 Semiconductor device with mode designation and substrate bias circuits
To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a...
US-9,646,678 Semiconductor integrated circuit device
Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with...
US-9,646,677 Semiconductor device and electronic device
Provided is a semiconductor device including first to fifth circuits. The first circuit includes first and second transistors. The second circuit is capable of...
US-9,646,675 Data training device and semiconductor device including the same
Disclosed are a data training device and a semiconductor device. The data training device includes a write controller configured to align write data, a read...
US-9,646,674 Data reception chip
A data reception chip coupled to an external memory comprising a first input-output pin to output first data and including a comparison module and a voltage...
US-9,646,673 Address detection circuit, memory system including the same
An address detection circuit includes an address storage unit suitable for receiving an address when an active command is activated, and storing recently...
US-9,646,672 Memory device and method of refreshing the same
A memory device includes a plurality of memory cells; a nonvolatile memory block suitable for simultaneously sensing one or more programmed weak addresses, and...
US-9,646,671 Systems and methods for managing write voltages in a cross-point memory array
Techniques are provided for managing voltages applied to memory cells in a cross-point array during a write operation (e.g., to transition from a resistive...
US-9,646,670 Spin-orbit-torque magnetoresistive random access memory with voltage-controlled anisotropy
Methods and apparatus relating to spin-orbit-torque magnetoresistive random access memory with voltage-controlled anisotropy are disclosed. In an example,...
US-9,646,669 Programming memory elements using two phase boost
Memory devices, such as MRAM devices, are described that comprise memory elements for storing data and configuration logic for programming memory elements using...
US-9,646,668 Spin-transfer torque magnetic random access memory (STTMRAM) with enhanced write current
A spin-transfer torque magnetic random access memory (STTMRAM) cell is disclosed. The memory cell comprises a selected magnetic tunnel junction (MTJ) identified...
US-9,646,667 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes: a first active area provided in a semiconductor substrate; a second active area provided in...
US-9,646,666 Voltage controlled spin switches for low power applications
Spin switch devices with voltage controlled magnetism in ultra-low power usage applications are disclosed. The spin switch devices may be configured to provide...
US-9,646,665 Look-up table circuit and nonvolatile memory device
A look-up table circuit of an embodiment includes: first wiring lines; second wiring lines; resistive change elements disposed to intersection regions of the...
US-9,646,664 Memory device and memory system including the same
A memory device may include a plurality of memory banks, a row control signal input unit suitable for receiving a plurality of row control signals, a column...
US-9,646,663 Multi-bank memory with line tracking loop
In some embodiments, a circuit comprises a plurality of memory banks, a column line tracking loop and/or a row line tracking loop, and a tracking circuit. The...
US-9,646,662 Apparatuses, circuits, and methods for biasing signal lines
Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled...
US-9,646,661 Memory device with internal combination logic
Embodiments of the present invention include an apparatus, method, and system for integrating data processing logic with memory. An embodiment of a memory...
US-9,646,660 Selectable memory access time
The present disclosure relates to selectable memory access time. An apparatus includes a memory controller. The memory controller is configured to select a...
US-9,646,659 Bitline senseamplifier and semiconductor memory apparatus using the same
A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and...
US-9,646,658 Sense amplifier and memory apparatus using the same
A sense amplifier includes a first input circuit, a second input circuit and an amplification circuit. The first input circuit may receive a pair of first input...
US-9,646,657 Power loss capacitor test using voltage ripple
These present disclosure provides techniques to determine the capacitance of a power loss capacitor based on voltage ripple. The power loss capacitor may be a...
US-9,646,656 Time-multiplexed communication protocol for transmitting a command and address between a memory controller and...
One embodiment sets forth a technique for time-multiplexed communication for transmitting command and address information between a controller and a multi-port...
US-9,646,655 Systems and methods for interaction-based analysis and visualization of remote collaboration sessions
Systems and methods of performing a process are provided, including receiving a live document video stream of a remote collaboration session, detecting a cursor...
US-9,646,654 Synchronization of events and audio or video content during recording and playback of multimedia content items
A computer-implemented method for simultaneously recording a media recording and an event recording includes recording a media recording, recording an event...
US-9,646,653 Techniques for processing and viewing video events using event metadata
A computing device for processing a video file. The video file comprises an audio track and contains at least one event comprising a scene of interest. One or...
US-9,646,652 Scene and activity identification in video summary generation based on motion detected in a video
Video and corresponding metadata is accessed. Events of interest within the video are identified based on the corresponding metadata, and best scenes are...
US-9,646,651 Marking stored video
A system for marking video comprises an input interface, a processor, and an output interface. The input interface is configured to receive event recorder data...
US-9,646,650 Automatically syncing recordings between two or more content recording devices
This disclosure generally relates to systems and methods that facilitate synchronizing recordings between a plurality of content recording devices using...
US-9,646,649 Medical image data information exchange system
[Problem] To efficiently and effectively exchange information on medical image data. [Solution] A video image extracted from a DICOM file is uploaded from an...
US-9,646,648 Method and apparatus for creating short video clips of important events
A method and apparatus for creating video clips is provided herein. During operation, a processing device will receive multiple video feeds from multiple video...
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