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Patent # Description
US-9,666,589 FinFET based flash memory cell
A method of manufacturing a semiconductor device is provided including providing a semiconductor substrate, forming a first plurality of semiconductor fins in a...
US-9,666,585 Method of manufacturing a semiconductor device having bit line structures disposed in trenches
Semiconductor devices are provided. The semiconductor device includes a bit line contact plug and a storage node contact plug electrically connected to an...
US-9,666,584 Method of manufacturing semiconductor integrated circuit device
Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain...
US-9,666,581 FinFET with source/drain structure and method of fabrication thereof
A method of semiconductor fabrication that includes providing a plurality of fins extending from a substrate is described. Each of the plurality of fins has a...
US-9,666,580 Nitride semiconductor device and method of manufacturing the same
A nitride semiconductor device includes a conductive substrate and a nitride semiconductor layer. The nitride semiconductor layer is disposed on the conductive...
US-9,666,575 Semiconductor arrangement facilitating enhanced thermo-conduction
A semiconductor arrangement includes a well region and a first region disposed within the well region. The first region includes a first conductivity type. The...
US-9,666,572 Process for forming package-on-package structures
A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the...
US-9,666,571 Package-on-package structures
Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a...
US-9,666,568 Photoelectric device and method of manufacturing the same
A photoelectric device includes an electrode structure, an LED (light emitting diode) element, a zener diode and a reflective cup. The LED element, the zener...
US-9,666,567 Light emitting device having underlying protective element
A light emitting device includes a base member; a light emitting element disposed on the base member via at least one first electrically conductive joining...
US-9,666,565 Optical device and method for manufacturing same
The present invention relates to an optical device and a method for manufacturing the same. The technical object of the invention is to realize a surface...
US-9,666,564 Light emitting device
A light emitting device includes a substrate, a plurality of micro light emitting chips, a plurality of reflective structures and a plurality of conductive...
US-9,666,563 Metal to metal bonding for stacked (3D) integrated circuits
The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked...
US-9,666,562 3D integrated circuit
A three-dimensional integrated circuit (3D-IC) architecture incorporates multiple layers, each layer including at least one die and at least one switch to...
US-9,666,561 Light emitting device package and lighting apparatus including the same
Alight emitting device package may include a printed circuit board and a plurality of light emitting devices mounted on the printed circuit board, wherein a...
US-9,666,560 Multi-chip microelectronic assembly with built-up fine-patterned circuit structure
A microelectronic assembly includes a dielectric element having bumps projecting from a first surface thereof, the bumps having end surfaces flush with a...
US-9,666,559 Multichip modules and methods of fabrication
In a multi-chip module (MCM), a "super" chip (110N) is attached to multiple "plain" chips (110F; "super" and "plain" chips can be any chips). The super chip is...
US-9,666,558 Substrate for mounting a chip and chip package using the substrate
Disclosed is a chip-mounting substrate. The chip-mounting substrate includes a plurality of conductive portions configured to apply voltages to at least two or...
US-9,666,557 Small footprint semiconductor package
A semiconductor assembly includes a substrate with electrically conductive regions and a semiconductor package. The semiconductor package includes a...
US-9,666,556 Flip chip packaging
An integrated circuit (IC) package includes a first substrate; a second substrate disposed over the first substrate; a plurality of connectors disposed between...
US-9,666,555 Manufacturing method of forming a semiconductor wafer structure
A method of manufacturing a semiconductor structure includes providing a first wafer including a surface, removing some portions of the first wafer over the...
US-9,666,553 Millimeter wave integrated circuit with ball grid array package including transmit and receive channels
A millimeter wave integrated circuit (IC) chip. The IC chip comprises an IC die and a wire bond ball grid array package encapsulating the IC die. The wire bond...
US-9,666,552 Semiconductor device connected by anisotropic conductive film
A semiconductor device connected by an anisotropic conductive film, the anisotropic conductive film including a polyurethane resin; at least one other resin...
US-9,666,550 Method and structure for wafer-level packaging
A method for wafer-level packaging includes providing a substrate having a conductive metal pad formed on the surface of the substrate; forming a metal core on...
US-9,666,543 Electronic system
An electronic system includes a carrier including at least one waveguide feeding, a semiconductor chip including a first surface and a second surface, and an...
US-9,666,537 Methods and apparatus using front-to-back alignment mark and placement for narrow wafer scribe lines
Methods and apparatus for front-to-back alignment using narrow scribe lines are disclosed. An apparatus is disclosed that includes a semiconductor wafer...
US-9,666,534 Semiconductor interconnect structure and manufacturing method thereof
The present disclosure provides an interconnect structure, including a low k dielectric layer with an air gap region and a non-air gap region. A first...
US-9,666,533 Airgap formation between source/drain contacts and gates
After forming a source/drain contact including a source/drain contact liner and a source/drain contact conductor surrounded by the source/drain contact liner to...
US-9,666,530 Semiconductor device
A semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a first dielectric over the semiconductor...
US-9,666,528 BEOL vertical fuse formed over air gap
A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the...
US-9,666,525 Three-dimensional semiconductor memory device
Three-dimensional (3D) semiconductor memory devices capable of improving reliability may be provided. For example, a three dimensional (3D) memory device, in...
US-9,666,521 Ultra high performance interposer
An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in...
US-9,666,519 Power semiconductor module and power unit
A power semiconductor module includes: a plurality of semiconductor element substrates disposed on the same plane, each of which includes an insulating...
US-9,666,516 Electronic packages and methods of making and using the same
An electronic package and a method of making the same in provided. The electronic package includes a dielectric layer and a conformal masking layer disposed on...
US-9,666,513 Wafer-level flipped die stacks with leadframes or metal foil interconnects
An assembly includes a plurality of stacked encapsulated microelectronic packages, each package including a microelectronic element having a front surface with...
US-9,666,511 Isolation method for a stand alone high voltage laterally-diffused metal-oxide semiconductor (LDMOS) transistor
A semiconductor package having a lead frame over which a first device and a second device are spaced is provided. The lead frame includes a die pad upon which a...
US-9,666,510 Dual row quad flat no-lead semiconductor package
Some of the embodiments of the present disclosure provide a Quad Flat No-Lead package comprising: an outer row of outer peripheral leads disposed on an outer...
US-9,666,505 Power MOS transistor die with temperature sensing function and integrated circuit
A power metal oxide semiconductor (MOS) transistor die with a temperature sensing function and an integrated circuit are provided. The power MOS transistor die...
US-9,666,503 Semiconductor package and electronic system including the same
A semiconductor package and an electronic system including the same include a package board having an electric circuit pattern. A semiconductor chip is mounted...
US-9,666,497 Crystal device
The crystal device has a rectangular substrate, a frame which is provided along the outer circumferential edge of the upper surface of the substrate, an...
US-9,666,496 Systems and methods for chemical mechanical planarization with photoluminescence quenching
A method includes performing a chemical-mechanical planarization (CMP) on an article, providing a polishing fluid including luminescent particles capable of...
US-9,666,491 Method of forming semiconductor device
A method of forming a semiconductor device includes following steps. Firstly, a first transistor is formed on a first surface of a substrate. Next, a thinning...
US-9,666,490 Multi-layer semiconductor structures for fabricating inverter chains
Methods for fabricating multiple inverter structures in a multi-layer semiconductor structure are provided. A first device layer is formed on a substrate. The...
US-9,666,489 Stacked nanowire semiconductor device
A semiconductor device a first epitaxially grown source/drain region comprising a first material arranged on a first fin, a second epitaxially grown...
US-9,666,483 Integrated circuit having thinner gate dielectric and method of making
An integrated circuit including a first transistor having a first gate dielectric layer with a first thickness. The integrated circuit also includes a second...
US-9,666,482 Self aligned silicon carbide contact formation using protective layer
A silicon-carbide substrate that includes a doped contact region and a dielectric layer is provided. A protective layer is formed on the dielectric layer. A...
US-9,666,480 Array substrate, method for manufacturing the same and method for measuring the same, display device
An array substrate comprising an electrical connection block exposed to its surface. By manufacturing a passivation layer via hole in a passivation layer, a...
US-9,666,479 Patterning method for low-k inter-metal dielectrics and associated semiconductor device
Semiconductor fabrication techniques and associated semiconductor devices are provided in which conductive lines are separated by a low dielectric constant...
US-9,666,476 Dimension-controlled via formation processing
Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s)...
US-9,666,472 Method for establishing mapping relation in STI etch and controlling critical dimension of STI
The present invention provides a method for controlling a critical dimension of shallow trench isolations in a STI etch process, comprises the following steps:...
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