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Patent # Description
US-9,665,510 Synchronous bus architecture for digital pre-distortion system
A system for storing pre-distorted output samples in a memory includes a sample counter, a programming interface module, and a comparator. The sample counter...
US-9,665,509 Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system
Apparatus and methods for handling inter-processor interrupts (IPIs) in a heterogeneous multiprocessor system are provided. The scalable IPI mechanism provided...
US-9,665,508 Method and an apparatus for converting interrupts into scheduled events
A method and an apparatus embodying the method for converting interrupts into scheduled events, comprising receiving an interrupt at an interrupt controller;...
US-9,665,507 Protocol including a command-specified timing reference signal
Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read...
US-9,665,506 Apparatus and method for processing data
A data processing device includes a controller. The controller includes a compression circuit configured to compare a plurality of data groups, each of which...
US-9,665,505 Managing buffered communication between sockets
A motherboard includes multiple sockets, each socket configured to accept an integrated circuit. A first integrated circuit in a first socket includes one or...
US-9,665,503 Efficient packet handling, redirection, and inspection using offload processors
A packet handling system is disclosed that can include at least one main processor; a plurality of offload processors connected to a memory bus and configured...
US-9,665,502 Virtual I/O hardware
Emulating a Fiber Channel connection to a workstation includes providing a first Fiber Channel emulator that exchanges data between the workstation and a data...
US-9,665,501 Self-encrypting data storage device supporting object-level encryption
A data storage device includes: a controller; an engine for performing at least one of encryption and decryption; and a logic circuit. In response to receiving...
US-9,665,500 System supporting multiple partitions with differing translation formats
A system configuration is provided with multiple partitions that supports different types of address translation structure formats. The configuration may...
US-9,665,499 System supporting multiple partitions with differing translation formats
A system configuration is provided with multiple partitions that supports different types of address translation structure formats. The configuration may...
US-9,665,498 Memory management using transparent page transformation
Memory space is managed to release storage area occupied by pages similar to stored reference pages. The memory is examined to find two similar pages, and a...
US-9,665,497 Methods and systems for performing a copy forward operation
A storage device made up of multiple storage media is configured such that one such media serves as a cache for data stored on another of such media. The device...
US-9,665,496 Non-volatile memory write mechanism
A system includes a memory buffer to cache a non-volatile memory. The non-volatile memory stores a plurality of valid and obsolete variables in a plurality of...
US-9,665,495 Methods and systems for throttling writes to a caching device in response to read misses
A storage device includes a flash memory-based cache for a hard disk-based storage device and a controller that is configured to limit the rate of cache updates...
US-9,665,494 Parallel lookup in first and second value stores
A data processing apparatus includes a cache memory supporting parallel data loads involving both a first address and a second address. The first address is...
US-9,665,493 Increased cache performance with multi-level queues of complete tracks
Exemplary method, system, and computer program product embodiments for increased cache performance using multi-level queues by a processor device. The method...
US-9,665,492 Fuzzy counters for NVS to reduce lock contention
A system for data management in a computing storage environment includes a processor device, operable in the computing storage environment, that divides a...
US-9,665,491 Adaptive mechanism to tune the degree of pre-fetches streams
According to one general aspect, a method may include monitoring a plurality of pre-fetch cache requests associated with a data stream. The method may also...
US-9,665,490 Apparatus and method for repairing cache arrays in a multi-core microprocessor
An apparatus includes a fuse array, a stores, and a plurality of cores. The fuse array is programmed with compressed configuration data. The stores is for...
US-9,665,489 Methods of selecting available cache in multiple cluster system
Aspects include computing devices, systems, and methods for implementing selecting an available shared cache memory as a victim cache. The computing device may...
US-9,665,488 Technique to share information among different cache coherency domains
A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches...
US-9,665,487 Intelligent snapshot point-in-time management in object storage
An application is used, by a processor, to provide directives to a tiered data object storage environment for manipulating and managing stored data objects by...
US-9,665,486 Hierarchical cache structure and handling thereof
A hierarchical cache structure comprises at least one higher level cache comprising a unified cache array for data and instructions and at least two lower level...
US-9,665,485 Logical and physical block addressing for efficiently storing data to improve access speed in a data...
One method includes assigning a pointer from multiple logical blocks to the same original physical block if the multiple logical blocks include the same data....
US-9,665,484 Electronic apparatus having nonvolatile memory and program writing method for updating
Provided is an electronic apparatus avoiding to be a starting failure status even if power off happens during the writing of a program. The electronic apparatus...
US-9,665,483 Method and apparatus for bit-interleaving
A manner of processing data for transmission in a data communication network. A node having a main memory and an interleaver is provided. Received data is...
US-9,665,482 System and method for selecting victim memory block for garbage collection
Embodiments of present disclosure disclose method and system for selecting victim memory block for garbage collection. A memory block having minimum valid unit...
US-9,665,481 Wear leveling method based on timestamps and erase counts, memory storage device and memory control circuit unit
A wear leveling method for a rewritable non-volatile memory module is provided. The method includes: recording a timestamp for each of physical erasing units...
US-9,665,480 Memory management method, memory storage device and memory control circuit unit
A memory management method, a memory storage device and a memory control circuit unit are provided. The memory management method includes: grouping a plurality...
US-9,665,479 Managing response time
Implementations disclosed herein provide for a method comprising receiving a read request to read data from a target die of a storage device, and rebuilding the...
US-9,665,478 Zone boundary adjustments for defects in non-volatile memories
A non-volatile memory is divided into logical zones by the card controller in order reduce the size of the data structures it uses for address translation. Zone...
US-9,665,477 Allocating additional requested storage space for a data set in a first managed space in a second managed space
Provided are a computer program product, system, and method for allocating additional requested storage space for a data set in a first managed space in a...
US-9,665,476 Auto-deployment and testing of system application test cases in remote server environments
A computer program product for executing a system application test case of a runtime system in a server environment is provided. The computer program product...
US-9,665,475 Application experiment system
Examples of an application experiment system are provided that can manage and run experiments for software applications. In one embodiment, the application...
US-9,665,474 Relationships derived from trace data
An analysis system may perform network analysis on data gathered from an executing application. The analysis system may identify relationships between code...
US-9,665,473 Smart tester application for testing other applications
A device may be configured to receive, from a first device, first test scripts for testing an application. The first test scripts may include information for...
US-9,665,467 Error and solution tracking in a software development environment
In an approach for error and solution tracking a processor identifies that a first occurrence of a first error is present in code. A processor tracks a first...
US-9,665,466 Debug architecture for multithreaded processors
Debug architecture for multithreaded processors. In some embodiments, a method includes, in response to receiving a halt command, saving a context of a thread...
US-9,665,465 Automated determination of application permissions
This disclosure describes, in part, a system and process that allows for the automated review of a submitted application to determine the actually requested...
US-9,665,464 System and method for running a validation process for an information handling system during a factory process
An information handling system includes a memory and a processor. The memory to store a script and an exemption list for a validation process, and the script...
US-9,665,463 In-process wrapped execution engine(s) for tooling a dynamic program across a process boundary
Techniques are described herein that are capable of instantiating and executing in-process wrapped execution engine(s) for tooling a dynamic program across a...
US-9,665,461 Obtaining application performance data for different performance events via a unified channel
A system for obtaining performance data for different performance events includes a first application monitoring performance of a second application executing...
US-9,665,460 Detection of abnormal resource usage in a data center
A system for identifying abnormal resource usage in a data center is provided. In some embodiments, the system employs a prediction model for each of a...
US-9,665,459 Providing a user interface to enable selection of storage systems, components within storage systems and common...
A storage system graphical user interface (GUI) renders indication of a plurality of selected storage systems. Selection is received of selected storage systems...
US-9,665,458 Method and system for providing information from third party applications to devices
A method and system of making information from an application accessible to an electronic device, comprising: checking, via a log monitor, a third party log...
US-9,665,457 Method for controlling process based on network operation mode and apparatus therefor
Disclosed are a method of controlling a process based on a network operation mode and an apparatus therefor. A process controlling method performed in a network...
US-9,665,456 Apparatus and method for identifying a cause of an error occurring in a network connecting devices within an...
An information processing apparatus includes a plurality of devices, each including a memory that stores link-status information indicating whether or not an...
US-9,665,455 Input module for programmable logic controller
The invention relates to an input module (32) for a programmable logic controller able to be connected to a plurality of elements of an automated chain, the...
US-9,665,454 Extracting test model from textual test suite
Computer-implemented method, computerized apparatus and computer program product for extracting test model from a textual test suite. The method comprises...
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