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Patent # Description
US-9,728,544 Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device may include forming split gate structures including a floating gate electrode layer and a control gate...
US-9,728,538 Three-dimensional devices having reduced contact length
Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with...
US-9,728,535 Methods of fabricating semiconductor devices including fin-shaped active regions
A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a...
US-9,728,534 Densely spaced fins for semiconductor fin field effect transistors
A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial...
US-9,728,529 Semiconductor device with electrostatic discharge protection structure
A semiconductor device comprises a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device...
US-9,728,526 Packaging of high performance system topology for NAND memory systems
A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the...
US-9,728,521 Hybrid bond using a copper alloy for yield improvement
An integrated circuit (IC) using a copper-alloy based hybrid bond is provided. The IC comprises a pair of semiconductor structures vertically stacked upon one...
US-9,728,520 Enhanced flash chip and method for packaging chip
An enhanced Flash chip and a method for packaging chip are provided to solve the problems of high design complexity. The enhanced Flash chip comprises: a FLASH...
US-9,728,512 Electro static discharge clamping device
Electrostatic discharge clamp devices are described. In one embodiment, the semiconductor device includes a first transistor, the first transistor including a...
US-9,728,490 Semiconductor devices and methods of manufacturing the same
A semiconductor device includes a via structure penetrating through a substrate, a portion of the via structure being exposed over a surface of the substrate, a...
US-9,728,488 Onboard electronic device
An onboard electronic device includes: an element that generates heat; a member that is provided between the element and a coolant cooling the element, and...
US-9,728,487 Semiconductor device
An object of the present invention is to improve the reliability of a semiconductor device having an imaging function. A semiconductor device includes a package...
US-9,728,484 Power module package and method for manufacturing the same
Disclosed relates to a power module package and a method for manufacturing the same. The power module package includes a lower substrate on which a pattern is...
US-9,728,478 Resin-encapsulatd semiconductor device and method of manufacturing the same
A first resin encapsulated body (25) and a second resin encapsulated body (26) are stacked to form a resin-encapsulated semiconductor device. The first resin...
US-9,728,468 Semiconductor device and manufacturing method thereof
A first well in a first conductivity type which is formed at a first region and is electrically connected to a first power supply line, a second well in a...
US-9,728,464 Self-aligned 3-D epitaxial structures for MOS device fabrication
Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within...
US-9,728,463 Methods of manufacturing semiconductor devices
Methods of manufacturing a semiconductor device are provided. The methods may include forming a fin-type active region protruding from a substrate and forming a...
US-9,728,462 Stable multiple threshold voltage devices on replacement metal gate CMOS devices
A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is...
US-9,728,457 System, structure, and method of manufacturing a semiconductor substrate stack
A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a...
US-9,728,454 Semiconductor structure and manufacturing method thereof
The present invention provides a semiconductor structure, includes a substrate, a dielectric layer disposed on the substrate, a first gate structure and a...
US-9,728,452 Method for depositing one or more polycrystalline silicon layers on substrate
A method for depositing one or more polycrystalline silicon layers (230c) on a substrate (210) by a chemical vapor deposition in a reactor, includes adjusting a...
US-9,728,451 Through silicon vias for semiconductor devices and manufacturing method thereof
The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first...
US-9,728,449 Semiconductor device structures with improved planarization uniformity, and related methods
Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a...
US-9,728,448 Method of manufacturing semiconductor device
Disclosed is a method of manufacturing a semiconductor device, including: forming a stacked structure including a plurality of layers, the stacked structure...
US-9,728,445 Method for forming conducting via and damascene structure
In accordance with some embodiments, a method for forming via holes is provided. The method includes providing a substrate with an etch stop layer and a...
US-9,728,440 Non-transparent microelectronic grade glass as a substrate, temporary carrier or wafer
A method for processing a semiconductor wafer where an opaque layer is located on a surface of a handling wafer is used so the surface of the handling wafer may...
US-9,728,438 Method for producing an electrostatic holding apparatus
Production of a holding apparatus (100) for electrostatically holding a component, e.g., silicon wafer (1), includes connecting plate-type first holding element...
US-9,728,437 High temperature chuck for plasma processing systems
A wafer chuck assembly includes a puck, a shaft and a base. An insulating material defines a top surface of the puck, a heater element is embedded within the...
US-9,728,435 Plating apparatus and plating method
A plating apparatus allows a substrate holder to be serviced easily while ensuring easy access to the substrate holder and while a substrate is being processed...
US-9,728,434 Substrate processing apparatus, storage device, and method of transporting substrate storing container
In a substrate processing apparatus, a storage device, an indexer block, a processing block and an interface block are arranged to line up in this order. The...
US-9,728,432 Method of degassing
A method of degassing semiconductor substrates includes sequentially loading a plurality of semiconductor substrates into a degas apparatus, and degassing the...
US-9,728,429 Parasitic plasma prevention in plasma processing chambers
Parasitic plasma in voids in a component of a plasma processing chamber can be eliminated by covering electrically conductive surfaces in an interior of the...
US-9,728,425 Space-efficient underfilling techniques for electronic assemblies
Space-efficient underfilling techniques for electronic assemblies are described. According to some such techniques, an underfilling method may comprise mounting...
US-9,728,424 Method of fabricating a packaged integrated circuit with through-silicon via an inner substrate
A method of manufacturing a semiconductor package includes forming a bonding layer on a carrier substrate, bonding an inner substrate to the carrier substrate,...
US-9,728,423 Piezoelectric thin film process
A process of forming an integrated circuit containing a piezoelectric thin film by forming a sol gel layer, drying in at least 1 percent relative humidity,...
US-9,728,422 Dry etching method
Disclosed is a dry etching method for a laminated film in which at least one silicon layer and at least one silicon oxide layer are laminated together. The dry...
US-9,728,420 Organic film composition, process for forming organic film, patterning process, and compound
An organic film composition including a compound represented by the following general formula (1), ##STR00001## wherein n1 and n2 each independently...
US-9,728,419 Fin density control of multigate devices through sidewall image transfer processes
Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a...
US-9,728,418 Etching method and etching apparatus
An etching method for performing a plasma etching on an object to be processed by using a supplied gas is provided. In the etching method, a temperature of a...
US-9,728,417 Method for processing base body to be processed
An exemplary embodiment provides a method which etches a second layer in a base body to be processed having a first layer containing Ni and Si and a second...
US-9,728,416 Plasma tuning rods in microwave resonator plasma sources
A resonator system is provided with one or more resonant cavities configured to couple electromagnetic (EM) energy in a desired EM wave mode to plasma by...
US-9,728,415 Semiconductor device and method of wafer thinning involving edge trimming and CMP
A semiconductor device has a substrate including a plurality of conductive vias formed vertically and partially through the substrate. An encapsulant is...
US-9,728,414 Method of depositing copper using physical vapor deposition
The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the...
US-9,728,413 Method for preparing film patterns
A method for preparing film patterns; firstly, a complementary film pattern (1) to a desired film pattern (201) is prepared on a substrate (3) with an erasable...
US-9,728,412 Integrated circuits with backside metalization and production method thereof
An embodiment of an integrated device, including a chip of semiconductor material wherein an integrated circuit is integrated, is proposed; the integrated...
US-9,728,411 Integrated circuits with backside metalization and production method thereof
An embodiment of an integrated device, including a chip of semiconductor material wherein an integrated circuit is integrated, is proposed; the integrated...
US-9,728,410 Split-gate non-volatile memory (NVM) cell and method therefor
A split gate memory device includes a semiconductor substrate and a select gate over the substrate. The select gate has a bottom portion and a top portion over...
US-9,728,409 Method of manufacturing semiconductor device
Provided is a method of manufacturing a semiconductor device, including: forming a stacked metal nitride film including a first metal nitride film and a second...
US-9,728,408 Method of semiconductor integrated circuit fabrication
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A dielectric layer is formed over a substrate. An interlayer is formed over the...
US-9,728,407 Method of forming features with various dimensions
A method of fabricating a semiconductor device is disclosed. The method includes forming mandrels over a material layer and forming spacers along sidewalls of...
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