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Patent # Description
US-9,735,265 Reduced area power devices using deep trench isolation
An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with...
US-9,735,264 Semiconductor switch with integrated temperature sensor
A semiconductor device includes a semiconductor body, at least one wiring layer disposed on the semiconductor body and a field effect transistor integrated in...
US-9,735,263 Transistor and switching system comprising silicon carbide and oxides of varying thicknesses, and method for...
An insulated gate field-effect transistor (IGFET) device includes a semiconductor body (200) and a gate oxide (234). The semiconductor body includes a first...
US-9,735,261 Semiconductor device and formation thereof
A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region...
US-9,735,260 III-V HEMT devices
A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed...
US-9,735,259 Method to build vertical PNP in a BiCMOS technology with improved speed
Various particular embodiments include an integrated circuit (IC) structure including: a stack region; and a silicon substrate underlying and contacting the...
US-9,735,258 Nanowire semiconductor device
A method for forming a nanowire device comprises depositing a hard mask on portions of a silicon substrate having a <110> orientation wherein the hard...
US-9,735,257 finFET having highly doped source and drain regions
A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin...
US-9,735,256 Method and structure for FinFET comprising patterned oxide and dielectric layer under spacer features
A semiconductor device and method of forming the same are disclosed. The method includes receiving a substrate having an active fin, an oxide layer over the...
US-9,735,255 Method for fabricating a finFET device including a stem region of a fin element
A method includes providing a substrate having a fin extending from a first (e.g., top) surface of the substrate. The fin has first region (a stem region) and a...
US-9,735,254 Trench-gate RESURF semiconductor device and manufacturing method
A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the...
US-9,735,253 Closely packed vertical transistors with reduced contact resistance
A method of forming a semiconductor device and resulting structures having closely packed vertical transistors with reduced contact resistance by forming a...
US-9,735,252 V-shaped SiGe recess volume trim for improved device performance and layout dependence
Some embodiments of the present disclosure relates to a method of forming a transistor device having a strained channel and an associated device. In some...
US-9,735,251 Semiconductor structure and fabrication method thereof
A method for forming a semiconductor structure includes providing a semiconductor substrate having a metal gate structure formed on the semiconductor substrate;...
US-9,735,250 Stable work function for narrow-pitch devices
A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the...
US-9,735,249 Gate structure with refractory metal barrier
Gate structures for semiconductor devices include a silicon nitride layer, an electron beam evaporated tantalum nitride layer disposed on the silicon nitride...
US-9,735,248 Pure boron for silicide contact
A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench...
US-9,735,247 High-frequency conductor having improved conductivity
A high-frequency conductor having improved conductivity comprises at least one electrically conductive base material. The ratio of the outer and inner surfaces...
US-9,735,246 Air-gap top spacer and self-aligned metal gate for vertical fets
Transistors and method of forming he same include forming a fin on a bottom source/drain region having a channel region and a sacrificial region on the channel...
US-9,735,245 Recessed salicide structure to integrate a flash memory device with a high .kappa., metal gate logic device
Some embodiments of the present disclosure provide an integrated circuit (IC) for an embedded flash memory device. The IC includes a flash memory cell having a...
US-9,735,244 Quasi-vertical structure having a sidewall implantation for high voltage MOS device and method of forming the same
A semiconductor device includes a buried layer in a substrate, the buried layer having a first dopant type. The semiconductor device further includes a first...
US-9,735,243 Semiconductor device, integrated circuit and method of forming a semiconductor device
A semiconductor device comprises a transistor formed in a semiconductor body having a first main surface. The transistor comprises a source region, a drain...
US-9,735,242 Semiconductor device with a gate contact positioned above the active region
One illustrative device disclosed herein includes a stepped conductive source/drain structure with a cavity defined therein, the cavity being located vertically...
US-9,735,241 Semiconductor device with a field plate double trench having a thick bottom dielectric
Disclosed is a power device, such as power MOSFET, and method for fabricating same. The device includes an upper trench situated over a lower trench, where the...
US-9,735,240 High electron mobility transistor (HEMT)
A high electron mobility transistor (HEMT) device with a highly resistive layer co-doped with carbon (C) and a donor-type impurity and a method for making the...
US-9,735,239 Semiconductor device channel system and method
A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary...
US-9,735,238 Avoiding internal switching loss in soft switching cascode structure device
In a cascode switching device, avalanche breakdown of a control transistor and loss of soft switching or zero voltage switching in a high voltage normally-on...
US-9,735,237 Active area designs for silicon carbide super-junction power devices
The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to active area designs for SiC super-junction (SJ)...
US-9,735,236 Quantum dot channel (QDC) quantum dot gate transistors, memories and other devices
This invention describes a field-effect transistor in which the channel is formed in an array of quantum dots. In one embodiment the quantum dots are cladded...
US-9,735,235 Nanowire and method of fabricating the same
A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed...
US-9,735,234 Stacked nanowire devices
A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is...
US-9,735,233 Electronic device including side gate and two-dimensional material channel and method of manufacturing the...
Provided are electronic devices and methods of manufacturing same. An electronic device includes an energy barrier forming layer on a substrate, an upper...
US-9,735,232 Method for manufacturing a semiconductor structure having a trench with high aspect ratio
The present disclosure provides a method for manufacturing a semiconductor structure. The method includes several operations as follows. A semiconductor...
US-9,735,231 Block layer in the metal gate of MOS devices
A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer,...
US-9,735,229 Semiconductor device
A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed...
US-9,735,228 Multilayer crown-shaped MIM capacitor and manufacturing method thereof
A multi-layer, crown-shaped MIM capacitor includes a base having therein conductive region, an inter-metal dielectric (IMD) layer on the base, a capacitor...
US-9,735,227 2D material super capacitors
Devices and methods are described relating to capacitor energy storage devices that are small in size and have a high energy stored to volume ratio. The...
US-9,735,226 Power module
Provided is a power module having a sufficient space in which a large electronic component in size is disposed, and having yield strength against external...
US-9,735,225 Chip resistor and electronic equipment having resistance circuit network
A compact and refined chip resistor, with which a plurality of types of required resistance values can be accommodated readily with the same design structure,...
US-9,735,224 Patterning magnetic films using self-stop electro-etching
A method of forming a semiconductor structure includes forming a seed layer over a top surface of a substrate and a protect layer over a top surface of the seed...
US-9,735,223 Organic light-emitting display apparatus and manufacturing method thereof
An organic light-emitting display apparatus and a manufacturing method thereof. The organic light-emitting display apparatus includes a substrate, a display...
US-9,735,222 Method for manufacturing circuit board, method for manufacturing light-emitting device,and light-emitting device
A circuit board in which damage to an electrode is reduced or a light-emitting device in which damage to an electrode is reduced is manufactured. A method for...
US-9,735,221 Display module
The display module includes first and second FPC substrates disposed on top of each other. The first substrate has an IC mounted on it. The second FPC substrate...
US-9,735,220 Display module
An organic display device includes a pixel driving circuit having a thin film transistor connected to a current supply line and a capacitor. A first insulation...
US-9,735,219 Organic light emitting diode display
An organic light emitting diode display includes: first gate wires provided on a substrate with a first insulation layer therebetween and extended in a first...
US-9,735,218 EL display device and method for manufacturing the same
A plurality of pixels are arranged on the substrate. Each of the pixels is provided with an EL element which utilizes as a cathode a pixel electrode connected...
US-9,735,217 Organic electroluminescent display device
An organic electroluminescent display device includes a display area including a plurality of pixels, a peripheral area as an area on the outside of the display...
US-9,735,216 Organic light emitting display device
An organic light emitting display (OLED) device is disclosed. The OLED device includes a substrate configured to include a sub-pixel defined into an emission...
US-9,735,215 Pixel demarcation layer, OLED and manufacturing method thereof as well as display device
A pixel demarcation layer includes a first pixel demarcation sub-layer and a second pixel demarcation sub-layer stacked on the first pixel demarcation...
US-9,735,214 Organic light emitting display device and manufacturing method thereof
An organic light emitting display (OLED) device, and a method for manufacturing the OLED device are discussed. The OLED device according to one embodiment...
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