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Patent # Description
US-9,735,161 Memory device and fabricating method thereof
A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a first active region, a second active region, a...
US-9,735,160 Method of co-integration of strained silicon and strained germanium in semiconductor devices including fin...
A method of forming a semiconductor device that includes forming an at least partially relaxed semiconductor material, and forming a plurality of fin trenches...
US-9,735,159 Optimized layout for relaxed and strained liner in single stress liner technology
An integrated circuit and method with a single stress liner film and a stress relief implant where the distance of the stress relief implant to the transistors...
US-9,735,158 Semiconductor devices having bridge layer and methods of manufacturing the same
A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on...
US-9,735,157 Semiconductor device and method of fabricating the same
A semiconductor device includes a first active area, a second active area and a first gate line. The second active area is spaced apart from the first active...
US-9,735,156 Semiconductor device and a fabricating method thereof
A semiconductor device including: a fin-type pattern protruding from a substrate and including a first side surface and a second side surface opposite each...
US-9,735,155 Bulk silicon germanium FinFET
A bulk SiGe FinFET which includes: a plurality of SiGe fins and a bulk semiconductor substrate, the SiGe fins extending from the bulk semiconductor substrate;...
US-9,735,154 Semiconductor structure having gap fill dielectric layer disposed between fins
Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a...
US-9,735,153 Semiconductor device having fin-type field effect transistor and method of manufacturing the same
A semiconductor device includes a first fin structure disposed on a substrate. The first fin structure extends in a first direction. A first sacrificial layer...
US-9,735,152 Non-planar structure with extended exposed raised structures and same-level gate and spacers
A starting non-planar semiconductor structure is provided having a semiconductor substrate, raised semiconductor structures coupled to the substrate, and a...
US-9,735,151 3D cross-point memory device
The present disclosure generally relates to semiconductor manufactured memory devices and methods of manufacture thereof. More specifically, methods for forming...
US-9,735,150 Semiconductor device and manufacturing method thereof
A semiconductor device includes an interlayer insulating film in which first contact holes and second contact holes are provided. Each of the second contact...
US-9,735,149 Schottky barrier diode
An SBD includes a semiconductor substrate; an anode electrode which is in Schottky contact with a front surface of the semiconductor substrate; and a cathode...
US-9,735,148 Semiconductor carrier with vertical power FET module
A monolithic power switch provides a semiconductor layer, a three dimensional FET formed in the semiconductor layer to modulate currents through the...
US-9,735,147 Fast and stable ultra low drop-out (LDO) voltage clamp device
In one general aspect, an apparatus can include a junction-less, gate-controlled voltage clamp device having a gate terminal coupled to a voltage reference device.
US-9,735,146 Vertical nanowire transistor for input/output structure
An electrostatic discharge (ESD) protection circuit includes an input terminal, a transistor, and an output terminal. The input terminal is configured to...
US-9,735,145 Electrostatic discharge protection for a balun
A die is mounted in an integrated circuit package. The die includes a balun circuit and an electrostatic discharge (ESD) circuit coupled to a ground of the...
US-9,735,144 Electrostatic discharge (ESD) protection device
An electrostatic discharge (ESD) protection device includes a semiconductor layer having a first doped region, a second doped region, and an intrinsic region...
US-9,735,143 Display substrate
A display substrate. The display substrate includes: a plurality of pixel units; a gate driving unit supplying a gate signal to the plurality of pixel units and...
US-9,735,142 Method of forming a protecting element comprising a first high concentration impurity region separated by an...
With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity....
US-9,735,141 Compound semiconductor transistor with gate overvoltage protection
A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound...
US-9,735,140 Systems and methods for a sequential spacer scheme
The present disclosure describes methods for transferring a desired layout into a target layer. The method includes a step of forming a spacer, having a second...
US-9,735,139 Optoelectronic device comprising a light-emitting diode
The invention relates to a method of manufacturing optoelectronic devices including light-emitting diodes, including the steps of: a) forming a first...
US-9,735,138 Integrated circuit package and method of making the same
A method of making an integrated circuit package includes: (a) forcing a circuit layered structure that includes a metal substrate and a circuit pattern, the...
US-9,735,137 Switch circuit package module
A switch circuit package module includes at least a semiconductor switch unit and at least a first capacitor unit. The semiconductor switch unit includes a...
US-9,735,136 Method for embedding silicon die into a stacked package
Several embodiments of microelectronic configurations with logic components and associated methods of manufacturing are disclosed herein. In one embodiment, the...
US-9,735,135 Optical sensor package and optical sensor assembly
There is provided an optical sensor package including a semiconductor base layer. A first surface of the semiconductor base layer is formed with a pixel array,...
US-9,735,134 Packages with through-vias having tapered ends
A package includes a device die, a molding material molding the device die therein, a through-via substantially penetrating through the molding material,...
US-9,735,133 Light-emitting device and lighting device provided with the same
A light-emitting device capable of ensuring an electric connection between a light-emitting element and an electrode without generating any problem in practical...
US-9,735,132 Semiconductor package
A semiconductor package includes a first chip, an insulating protection layer, a second chip, a plurality of second conductive bumps and an underfill. The...
US-9,735,131 Multi-stack package-on-package structures
A package includes a first device die, and a first encapsulating material encapsulating the first device die therein. A bottom surface of the first device die...
US-9,735,130 Chip packages and methods of manufacture thereof
A chip package may include: a first die; at least one second die disposed over the first die; and a lid disposed over lateral portions of the first die and at...
US-9,735,129 Semiconductor packages and methods of forming the same
Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first...
US-9,735,128 Method for incorporating stress sensitive chip scale components into reconstructed wafer based modules
Techniques for constructing an electronic module are provided herein. For example, the techniques include orienting at least one die having a top side (e.g., a...
US-9,735,127 Semiconductor device and electronic device
An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted. The first and second...
US-9,735,126 Solder alloys and arrangements
A solder alloy is providing, the solder alloy including zinc, aluminum, magnesium and gallium, wherein the aluminum constitutes by weight 8% to 20% of the...
US-9,735,124 Semiconductor structure and method of fabricating the same
The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads,...
US-9,735,123 Semiconductor device structure and manufacturing method
A semiconductor device structure and a manufacturing method are provided. The method includes forming a conductive pillar over a semiconductor substrate. The...
US-9,735,122 Flip chip package structure and fabrication process thereof
Disclosed herein are various chip packaging structures and methods of fabrication. In one embodiment, a flip chip package structure can include: (i) a pad on a...
US-9,735,121 Semiconductor chip, semiconductor package including the same, and method of fabricating the same
A semiconductor chip and/or a semiconductor package including the same are disclosed. The semiconductor chip may include an integrated circuit on a substrate, a...
US-9,735,120 Low z-height package assembly
In embodiments, a package assembly may include a die coupled with one or more conductive pads. A barrier layer may be directly coupled with and between the die...
US-9,735,119 Conductive pads forming method
In some embodiments, the present disclosure provides a conductive pads forming method. The conductive pads forming method may include providing a contact pad or...
US-9,735,118 Antennas and waveguides in InFO structures
A method includes forming a first metal plate, forming a metal ring aligned to peripheral regions of the first metal plate, and placing a device die level with...
US-9,735,117 Devices and methods related to interconnect conductors to reduce de-lamination
Disclosed are systems, devices and methods for utilizing an interconnect conductor to inhibit or reduce the likelihood of de-lamination of a passivation layer...
US-9,735,116 Seal ring structure to avoid delamination defect
A semiconductor device includes a semiconductor substrate, a plurality of integrated circuit devices on the semiconductor substrate, and a seal ring structure...
US-9,735,115 Image pickup apparatus and camera module
An image pickup apparatus includes an optical device, a transparent conductive film, an electrode pad, and a penetrating electrode. In the optical device, an...
US-9,735,114 Method of packaging semiconductor device
A first insulation layer comprising stacked prepreg layers is provided, and a metallic protective layer is formed on the first insulation layer. A first...
US-9,735,113 Semiconductor device and method of forming ultra thin multi-die face-to-face WLCSP
A semiconductor device has a first semiconductor die stacked over a second semiconductor die which is mounted to a temporary carrier. A plurality of bumps is...
US-9,735,112 Isolation between semiconductor components
In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the...
US-9,735,111 Dual metal-insulator-semiconductor contact structure and formulation method
A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain...
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