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Patent # Description
US-9,735,110 Semiconductor device and semiconductor device manufacturing method
A semiconductor device according to the present invention includes a semiconductor substrate, and an interlayer dielectric film, formed on the semiconductor...
US-9,735,109 Semiconductor device and semiconductor device manufacturing method
To restrict the deterioration of properties in a semiconductor device due to hydrogen, provided is a semiconductor device including a semiconductor substrate; a...
US-9,735,108 Line structure and a method for producing the same
A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer...
US-9,735,107 Contact structure and formation thereof
A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the...
US-9,735,106 Semiconductor lead frame, semiconductor package, and manufacturing method thereof
A semiconductor lead frame includes a metal plate and a semiconductor chip mounting area provided on a top surface of the metal plate. A first plating layer for...
US-9,735,105 Integrated secure device
According to an example aspect of the present invention, there is provided an apparatus comprising a silicon layer comprising security circuitry and a first...
US-9,735,104 Fuse structure having multiple air dummy fuses
A fuse structure includes a fusing line including a first portion, a second portion, and a central portion between the first portion and the second portion; and...
US-9,735,103 Electrical antifuse having airgap or solid core
An antifuse structure including an opening through a dielectric material to a contact surface and an antifuse material layer present within the opening. The...
US-9,735,102 High voltage device
Devices and methods of forming a device are disclosed. The method includes providing a wafer that includes a center insulator layer sandwiched by a top...
US-9,735,101 Semiconductor device with through-substrate via covered by a solder ball
The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of...
US-9,735,100 Semiconductor device and method of manufacturing the same
A semiconductor device according to the present invention includes a plurality of semiconductor chips, a plate electrode disposed on the plurality of...
US-9,735,099 Wiring substrate, semiconductor device and method for manufacturing semiconductor device
A wiring substrate used for improvement in manufacturing efficiency of a semiconductor device includes a support body having transparency; an adhesive layer...
US-9,735,098 Wiring substrate and semiconductor device
A wiring substrate including an insulation layer, a connection terminal projecting from an upper surface of the insulation layer, a protective insulation layer...
US-9,735,097 Package substrate, method for making the same, and package structure having the same
A package substrate includes a first conductive wire layer having a first end portion and a second end portion opposite to the first end portion. A width of the...
US-9,735,096 Lead frame and method for manufacturing the same
A metal plate 1 to be a lead frame has a plating with Sn or Zn or a plating with various alloys containing these metals only on the side faces and half-etched...
US-9,735,095 Semiconductor component and method of manufacture
In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device...
US-9,735,094 Combined packaged power semiconductor device
A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal...
US-9,735,093 Stacked chip-on-board module with edge connector
A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module...
US-9,735,092 Manufacturing method of chip package structure
A manufacturing method of a chip package structure includes following steps. A substrate including a first metal layer, a second metal layer, and an insulation...
US-9,735,091 Package structure and manufacturing method thereof
The invention discloses a package structure for better heat-dissipation or EMI performance. A first conductive element and a second conductive element are both...
US-9,735,090 Integrated circuit devices having through-silicon vias and methods of manufacturing such devices
An integrated circuit device includes a semiconductor structure, a through-silicon-via (TSV) structure that penetrates through the semiconductor structure and a...
US-9,735,089 Thermal management for flexible integrated circuit packages
Disclosed herein are systems and methods for thermal management of a flexible integrated circuit (IC) package. In some embodiments, a flexible IC package may...
US-9,735,088 Systems and methods for thermal control of integrated circuits
A system includes a carrier defining a plurality of channels. The system includes an integrated circuit (IC) die having a first side and having a second side...
US-9,735,087 Wafer level embedded heat spreader
Disclosed herein are a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer, a...
US-9,735,086 Power semiconductor module having a two-part housing
A power semiconductor module includes a substrate having a first side for being arranged to face a heat sink and for being thermally conductively connected to...
US-9,735,085 Bonded body, power module substrate, power module and method for producing bonded body
There is provided a bonded body of the invention in which a ceramic member formed of a ceramic containing Al and a Cu member formed of Cu or a Cu alloy are...
US-9,735,084 Bond via array for thermal conductivity
In a microelectronic device, a substrate has first upper and lower surfaces. An integrated circuit die has second upper and lower surfaces. Interconnects couple...
US-9,735,083 Adjustable heat sink fin spacing
A heat sink includes a heat sink base, a first fin, and a second fin. The spacing between the base and the first fin and the second fin, restively, may be...
US-9,735,082 3DIC packaging with hot spot thermal management features
A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and...
US-9,735,081 Semiconductor device
A semiconductor device capable of carrying out temperature detection appropriately by a temperature sensor is provided. In a semiconductor device disclosed...
US-9,735,080 Single-layer wiring package substrate, single-layer wiring package structure having the package substrate, and...
A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a...
US-9,735,079 Molding compound wrapped package substrate
A package substrate for chip/chips package wrapped by a molding compound is disclosed. The molding compound functions as a stiffener for the thin film package...
US-9,735,078 Device including multiple semiconductor chips and multiple carriers
A device includes a first semiconductor chip that is arranged over a first carrier and includes a first electrical contact. The device further includes a second...
US-9,735,077 Heterogeneous miniaturization platform
A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory...
US-9,735,076 Epoxy resin composition for encapsulating semiconductor device and semiconductor device encapsulated by the same
An epoxy resin composition for encapsulating a semiconductor device and a semiconductor device encapsulated by the epoxy resin composition, the composition...
US-9,735,075 Electronic module and fabrication method thereof
An electronic module is provided, including an electronic element and a strengthening layer formed on a side surface of the electronic element but not formed on...
US-9,735,074 Semiconductor device
Disclosed is a semiconductor device that is configured to contain a sealing layer for sealing a semiconductor element supported on a base, the sealing layer...
US-9,735,073 TFT switch and method for manufacturing the same
A thin-film transistor (TFT) switch includes a gate, a drain, a source, a semiconductor layer, and a fourth electrode. The drain is connected to a first signal....
US-9,735,072 Method for producing a plurality of measurement regions on a chip, and chip with measurement regions
A a chip and a method for producing the chip with a plurality of measurement regions which are provided with electrodes for electrically detecting reactions in...
US-9,735,071 Method of forming a temporary test structure for device fabrication
A method of forming a temporary test structure for device fabrication is provided. The method is particularly useful for electrically testing conductive...
US-9,735,070 Methods of manufacturing light source module
Manufacturing a light source module may include mounting light emitting devices on substrates on an upper surface of a carrier, mounting optical devices to...
US-9,735,069 Method and apparatus for determining process rate
A method for dry processing a substrate in a processing chamber is provided. The substrate is placed in the processing chamber. The substrate is dry processed,...
US-9,735,068 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes receiving film thickness distribution data of a polished first insulating film of a substrate;...
US-9,735,067 Substrate tuning system and method using optical projection
Techniques herein include systems and methods that provide a spatially-controlled or pixel-based projection of light onto a substrate to tune various substrate...
US-9,735,066 Surface delayering with a programmed manipulator
A method and apparatus for use in surface delayering for fault isolation and defect localization of a sample work piece is provided. More particularly, a method...
US-9,735,065 Systems and methods of local focus error compensation for semiconductor processes
A system and method of compensating for local focus errors in a semiconductor process. The method includes providing a reticle and applying, at a first portion...
US-9,735,064 Charge dynamics effect for detection of voltage contrast defect and determination of shorting location
A method and apparatus for detecting VC defects and determining the exact shorting locations based on charging dynamics induced by scan direction variation are...
US-9,735,063 Methods for forming fin structures
A method includes providing a substrate having a first and a second plurality of fins with a first at least one dielectric material disposed thereon, removing...
US-9,735,062 Defect reduction in channel silicon germanium on patterned silicon
After forming a blanket silicon germanium (SiGe) layer over a thinned silicon (Si) layer of a silicon-on-insulator (SOI) substrate, a portion of the SiGe layer...
US-9,735,061 Methods to form multi threshold-voltage dual channel without channel doping
Methods to form multi V.sub.t channels, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices are disclosed....
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