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Patent # Description
US-9,735,060 Hybrid fin cut etching processes for products comprising tapered and non-tapered FinFET semiconductor devices
For an integrated circuit product comprising a non-tapered FinFET device formed in a first region of the substrate and a tapered FinFET device in a second...
US-9,735,059 Method of fabricating semiconductor device including an etch barrier pattern
A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region...
US-9,735,058 Method of forming performance optimized gate structures by silicidizing lowered source and drain regions
A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type...
US-9,735,057 Fabricating field effect transistor(s) with stressed channel region(s) and low-resistance source/drain regions
Methods of fabricating field effect transistors having a source region and a drain region separated by a channel region are provided which include: using a...
US-9,735,056 Semiconductor piece manufacturing method and substrate dicing method for suppressing breakage
A semiconductor piece manufacturing method includes: a process of forming a groove on a front surface side including a first groove portion having a first width...
US-9,735,055 Electronic circuit unit and method of manufacturing electronic circuit unit
An electronic circuit unit includes a circuit substrate having a rectangular shape and is obtained by cutting an integral substrate along a vertical cut line...
US-9,735,054 Gate tie-down enablement with inner spacer
A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner...
US-9,735,053 Source driving integrated circuits including an electrostatic discharge circuit and related layout method
A source driving integrated circuit is provided. The source driving integrated circuit includes a source driver area, an electrostatic discharge (ESD) circuit...
US-9,735,052 Metal lines for interconnect structure and method of manufacturing same
A method for fabricating a semiconductor device includes forming a dielectric layer over a substrate, forming an etch-stop-layer (ESL) over the dielectric...
US-9,735,051 Semiconductor device interconnect structures formed by metal reflow process
Methods are devices are provided in which interconnection structures are formed using metal reflow techniques. For example, a method to fabricate a...
US-9,735,050 Composite contact plug structure and method of making same
An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer...
US-9,735,049 Method for fabricating semiconductor structure with passivation sidewall block
A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes receiving a substrate with two sections of...
US-9,735,048 Semiconductor device and fabricating process for the same
A semiconductor device and a fabricating process for the same are provided. The semiconductor device includes a base layer having a part of a reactive material;...
US-9,735,047 Semiconductor device and method for fabricating the same
A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a...
US-9,735,046 Semiconductor device manufacturing method and storage medium
A method of manufacturing a semiconductor device includes preparing a substrate having an interlayer insulating film and a hard mask provided on the interlayer...
US-9,735,045 Method of fabricating SOI wafer by ion implantation
The present invention provides a method of manufacturing a bonded wafer, including performing RTA under an atmosphere containing hydrogen on a bonded wafer...
US-9,735,044 Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a polymer substrate and an interfacial layer over...
US-9,735,043 Semiconductor packaging structure and process
A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to...
US-9,735,041 Universal clamping fixture to maintain laminate flatness during chip join
A clamping apparatus and method for maintaining a workpiece flatness during processing includes a base having a planar surface for receiving a first workpiece....
US-9,735,040 Method of processing single-crystal substrate
A method of dividing a single-crystal substrate along a plurality of preset division lines, includes a shield tunnel forming step of applying a pulsed laser...
US-9,735,039 Apparatus for separating wafer from carrier
An apparatus for separating a wafer from a carrier includes a platform having an upper surface, a tape feeding unit, a first robot arm, and a controller coupled...
US-9,735,038 Process for manufacturing a semiconductor structure with temporary bonding via metal layers
A method for manufacturing a structure implementing temporary bonding a substrate to be handled with a handle substrate, including: providing the substrate to...
US-9,735,037 Locally heated multi-zone substrate support
Embodiments of the present disclosure provide an electrostatic chuck (ESC) having azimuthal temperature control. In one embodiment, the electrostatic chuck...
US-9,735,036 System and method for aligning a wafer for fabrication
Described are computer-based methods and apparatuses, including computer program products, for aligning a wafer for fabrication. A first image of a first...
US-9,735,035 Methods and apparatuses for estimating on-wafer oxide layer reduction effectiveness via color sensing
Disclosed are methods of preparing a semiconductor substrate having a metal seed layer for a subsequent electroplating operation. In some embodiments, the...
US-9,735,034 Visual feedback for process control in RTP chambers
Embodiments of the present disclosure generally relate to methods and apparatus for visual lamp failure detection in a processing chamber, such as an RTP...
US-9,735,033 Multiple swivel arm design in hybrid bonder
An apparatus for cleaning a wafer includes a wafer station configured to hold the wafer, and a first and a second dispensing system. The first dispensing system...
US-9,735,032 System and method for manufacturing a fabricated carrier
A method of fabricating a BGA carrier, the method comprising combining a conductive portion and a molded dielectric portion, the dielectric portion having a top...
US-9,735,031 Polishing compositions and methods for polishing cobalt films
The present disclosure relates to polishing compositions that can polish Cobalt (Co) films in semiconductor substrates containing a multitude of films including...
US-9,735,030 Polishing compositions and methods for polishing cobalt films
The present disclosure relates to polishing compositions that can polish Cobalt (Co) films in semiconductor substrates containing a multitude of films including...
US-9,735,029 Metal fill optimization for self-aligned double patterning
A technique relates to a method of optimizing self-aligned double patterning. Predefined locations for required metal cuts are provided in order to form metal...
US-9,735,028 Method for forming semiconductor device structure with fine line pitch and fine end-to-end space
A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a...
US-9,735,027 Method for etching organic film
Disclosed is a method for etching an organic film. Plasma of a processing gas containing hydrogen gas and nitrogen gas is generated within a processing...
US-9,735,026 Controlling cleaning of a layer on a substrate using nozzles
Provided is a method for cleaning an ion implanted resist layer or a substrate after an ashing process. A duty cycle for turning on and turning off flows of a...
US-9,735,025 Etching method
A method of etching a first region including a multilayered film, in which first dielectric films and second dielectric films serving as silicon nitride films...
US-9,735,024 Method of atomic layer etching using functional group-containing fluorocarbon
A method of atomic layer etching (ALE) uses a cycle including: continuously providing a noble gas; providing a pulse of an etchant gas to the reaction space to...
US-9,735,023 Methods for manufacturing block copolymer compositions and articles manufactured therefrom
Disclosed herein is a composition comprising a first block copolymer that comprises a first block and a second block; where the first block has a higher surface...
US-9,735,022 Arrays of long nanostructures in semiconductor materials and methods thereof
An array of nanowires and method thereof. The array of nanowires includes a plurality of nanowires. The plurality of nanowires includes a plurality of first...
US-9,735,021 Etching method
An etching method of etching a first region including a multilayered film, in which silicon oxide films and silicon nitride films are alternately stacked, and a...
US-9,735,020 System, method and apparatus for plasma etch having independent control of ion generation and dissociation of...
A method of etching a wafer includes injecting a source gas mixture into a process chamber. The injecting includes injecting the source gas into multiple hollow...
US-9,735,019 Process gas enhancement for beam treatment of a substrate
A beam processing system and method of operating are described. In particular, the beam processing system includes a beam source having a nozzle assembly that...
US-9,735,018 Extremely thin package
Techniques for achieving extremely thin package structures are disclosed. In some embodiments, a device comprises an integrated circuit connected to a leadframe...
US-9,735,017 Method of manufacturing semiconductor device
A false report on appearance inspection of a semiconductor device is prevented by suppressing variation in surface state of an electrodeposited gold electrode....
US-9,735,016 Semiconductor device, method of fabricating the same, and apparatus used in fabrication thereof
A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper...
US-9,735,015 Fabricating method of semiconductor structure
A method of manufacturing a semiconductor structure, comprising: providing a preliminary structure having a first region and a second region and comprising a...
US-9,735,014 Memory device
A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper...
US-9,735,013 Ion implantation for improved contact hole critical dimension uniformity
Provided herein are approaches for patterning a semiconductor device. In an exemplary approach, a method includes providing a set of contact openings through a...
US-9,735,012 Short-channel nFET device
A method of forming a semiconductor device is provided including co-implanting a halo species and carbon in a semiconductor layer with a finite tilt angle with...
US-9,735,011 Metal interconnect structure and fabrication method thereof
A method is provided for fabricating a metal interconnect structure. The method includes forming a reticle having a metal line pattern region and at least a...
US-9,735,010 Fabrication of semiconductor fin structures
A semiconductor substrate is a provided and an insulating layer is formed thereon. A cavity structure is formed above the insulating layer, including a lateral...
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