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Patent # Description
US-9,734,093 Management of secured storage devices in an information handling system
Systems and methods for managing secured storage devices in an Information Handling System (IHS) are described. In some embodiments, a Baseboard Management...
US-9,734,092 Secure support for I/O in software cryptoprocessor
Methods and systems for securing sensitive data from security risks associated with direct memory access ("DMA") by input/output ("I/O") devices are provided....
US-9,734,091 Remote load and update card emulation support
Remote load and update card emulation support may include providing emulation support for an emulated card by executing a command set from command sets that...
US-9,734,090 Partitioned reference counter
Resource use is recorded with a partitioned reference counter. The sum of all resource counter partitions is equivalent to the total references to a resource....
US-9,734,089 Memory management unit and method for accessing data
A method for accessing data blocks stored in a computer system. The method may include hardware components for controlling access to a memory unit of the...
US-9,734,088 Memory management unit and method for accessing data
A method for accessing data blocks stored in a computer system. The method may include hardware components for controlling access to a memory unit of the...
US-9,734,087 Apparatus and method for controlling shared cache of multiple processor cores by using individual queues and...
A control unit stores data used in a process to a shared cache memory. The control unit provides a shared queue in a memory space of the shared cache memory and...
US-9,734,086 Apparatus, system, and method for a device shared between multiple independent hosts
The invention includes a proxy request receiver module and a proxy request command module. The proxy request receiver module executes on a designated command...
US-9,734,085 DMA transmission method and system thereof
A method for transmitting data between an information processing device and a storage device, in which the storage device includes a buffer memory and flash...
US-9,734,084 Separate memory address translations for instruction fetches and data accesses
An address translation capability in which a processor obtains an address to be translated, and translates the address from the address to the another address....
US-9,734,083 Separate memory address translations for instruction fetches and data accesses
An address translation capability in which a processor obtains an address to be translated, and translates the address from the address to the another address....
US-9,734,082 Temporal standby list
In one embodiment, a memory management system temporarily maintains a memory page at an artificially high priority level. The memory management system may...
US-9,734,081 Thin provisioning architecture for high seek-time devices
A compute server accomplishes physical address to virtual address translation to optimize physical storage capacity via thin provisioning techniques. The thin...
US-9,734,080 Cache organization and method
A method and information processing system with improved cache organization is provided. Each register capable of accessing memory has associated metadata,...
US-9,734,079 Hybrid exclusive multi-level memory architecture with memory management
Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller...
US-9,734,078 Resetting memory locks in a transactional memory system
A method for resetting of memory locks in a transactional memory system. The method includes a processor setting at least one new memory lock during execution...
US-9,734,077 Sending packets using optimized PIO write sequences without sfences
Method and apparatus for sending packets using optimized PIO write sequences without sfences. Sequences of Programmed Input/Output (PIO) write instructions to...
US-9,734,076 Dynamically changing a buffer flush threshold of a tape drive based on historical transaction size
A method for dynamically changing a buffer threshold in a tape drive, according to another embodiment, includes monitoring a history of sizes of data...
US-9,734,075 Cache memory control program, processor incorporating cache memory, and cache memory control method
A cache memory control procedure has: cache area allocating including allocating, in response to an acquisition request, and according to an effective cache...
US-9,734,074 Data copy avoidance across a storage
Embodiments of the present disclosure relate to methods and apparatuses for data copy avoidance where after a data access request is received from the first...
US-9,734,073 System and method for flash read cache with adaptive pre-fetch
Systems and methods for improved flash memory performance in a portable computing device are presented. In a method, a value N corresponding to an amount of...
US-9,734,072 Main memory prefetch operation and multiple prefetch operation
Provided is an integrated circuit that includes a first prefetcher component communicatively coupled to a processor and a second prefetcher component...
US-9,734,071 Method and apparatus for history-based snooping of last level caches
A method and apparatus for snooping caches is disclosed. In one embodiment, a system includes a number of processing nodes and a cache shared by each of the...
US-9,734,070 System and method for a shared cache with adaptive partitioning
A cache controller adaptively partitions a shared cache. The adaptive partitioning cache controller includes tag comparison and staling logic and selection...
US-9,734,069 Multicast tree-based data distribution in distributed shared cache
Systems and methods for multicast tree-based data distribution in a distributed shared cache. An example processing system comprises: a plurality of processing...
US-9,734,068 Cost sensitive browser cache cleanup based on weighted probabilistic cached item usage
For browser cache cleanup, to consider for eviction a data item stored in a cache of a browser application in a device, a probability that the data item will be...
US-9,734,066 Workload-based adjustable cache size
A workload level associated with an expandable data buffer is determined, where the expandable data buffer and an expandable mapping table cache are stored in...
US-9,734,065 Method of managing consistency of caches
The present invention relates to a method of transmitting a message comprising an integrity check and a header, between two processing units via a shared...
US-9,734,064 System and method for a cache in a multi-core processor
The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores,...
US-9,734,063 Scale-out non-uniform memory access
A computing system that uses a Scale-Out NUMA ("soNUMA") architecture, programming model, and/or communication protocol provides for low-latency, distributed...
US-9,734,062 System and methods for caching a small size I/O to improve caching device endurance
An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache comprises one or...
US-9,734,061 Memory control circuit and processor
A memory control circuit has a request determination circuitry to determine whether a period without read-out request and write request to an i-th (i being an...
US-9,734,060 Electronic device and method for fabricating the same
An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the...
US-9,734,059 Methods and apparatus for data cache way prediction based on classification as stack data
A method of way prediction for a data cache having a plurality of ways is provided. Responsive to an instruction to access a stack data block, the method...
US-9,734,058 Optimizing configuration memory by sequentially mapping the generated configuration data by determining regular...
A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the...
US-9,734,057 Semiconductor storage device and buffer operation method thereof
A method of operating a semiconductor storage device is provided. A memory space of a buffer memory is allocated into a data area for storing user data and a...
US-9,734,056 Cache structure and management method for use in implementing reconfigurable system configuration information...
A cache structure for use in implementing reconfigurable system configuration information storage, comprises: layered configuration information cache units: for...
US-9,734,055 Information processing apparatus and access control method
Upon receipt of an instruction to access a logical address of a storage medium, an information processing apparatus controls access to its corresponding...
US-9,734,054 Efficient implementation of geometric series
Methods and apparatus related to efficient implementation of geometric series are discussed herein. For example, memory stores data corresponding to a geometric...
US-9,734,053 Garbage collection handler to update object pointers
Garbage collection processing is facilitated. Based on execution of a load instruction and determining that an object pointer to be loaded indicates a location...
US-9,734,052 Multi-section garbage collection
The embodiments relate to a method for managing a garbage collection process. The method includes executing a garbage collection process on a memory block of...
US-9,734,051 Garbage collection and defragmentation for solid state drives (SSD) and shingled magnetic recording (SMR) drives
Example apparatus and methods provide improved reclamation, garbage collection (GC) and defragmentation (defrag) for data storage devices including solid state...
US-9,734,050 Method and system for managing background operations in a multi-layer memory
A multi-layer memory and method for performing background maintenance operations are disclosed. The memory includes a plurality of flash memory die having...
US-9,734,049 Relocating data in a memory device
Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory...
US-9,734,048 Storage management device, performance adjustment method, and computer-readable recording medium
A receiving unit receives an input of information of a performance level with respect to a volume that is allocated by using different types of disks. A target...
US-9,734,047 Method and apparatus for an improved automated test of software with a graphical user interface
A method for performing an automated computer test. The automated test is configured to cause a test computer system to control a GUI of a system under test...
US-9,734,046 Recording, replaying and modifying an unstructured information management architecture (UIMA) pipeline
The technique herein substantially improves productivity of Annotator developers by providing methods and systems to develop and test Annotators without having...
US-9,734,045 Generating test cases
Systems and techniques are described for generating test cases. A described technique includes monitoring a manual test of a code portion. The monitoring can...
US-9,734,044 Automatic test case generation
According to an embodiment of the present invention, a system for generating one or more test cases for a service of a server system comprises at least one...
US-9,734,043 Test selection
In a method for selecting one or more tests for a compiled software module, a processor detects that one or more changes have been made to source code for a...
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