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Patent # Description
US-9,741,666 Electromagnetic wall in millimeter-wave cavity
An apparatus includes a package, a wall and a lid. The package may be configured to mount two chips configured to generate one or more signals in a...
US-9,741,665 Alignment marks in non-STI isolation formation and methods of forming the same
A method includes forming a photo resist over a semiconductor substrate of a wafer, patterning the photo resist to form a first opening in the photo resist, and...
US-9,741,664 High density substrate interconnect formed through inkjet printing
Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a...
US-9,741,663 Semiconductor device and manufacturing method thereof
According to one embodiment, a semiconductor device includes an underlayer formed on a substrate, a catalyst layer disposed on the underlayer and extending in...
US-9,741,662 Semiconductor device and method of manufacturing the same, and power supply apparatus
A semiconductor device includes an electrode material diffusion suppression layer provided either between a gate electrode and a gate insulation film, between...
US-9,741,661 Logic semiconductor devices
A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical...
US-9,741,659 Electrical connections for chip scale packaging
Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a...
US-9,741,658 Electrical fuse structure and method of formation
A fuse device having contacts configured to reduce electro-migration is disclosed. In some exemplary embodiments, the fuse structure includes an anode disposed...
US-9,741,657 TSV deep trench capacitor and anti-fuse structure
A through-silicon-via (TSV) structure is formed within a trench located within a semiconductor structure. The TSV structure may include a first electrically...
US-9,741,656 High-frequency integrated device with an enhanced inductance and a process thereof
The present invention provides a high-frequency integrated device, comprising a substrate including at least an on-chip active and passive member and a ferrite...
US-9,741,655 Integrated circuit common-mode filters with ESD protection and manufacturing method
An integrated circuit common-mode electromagnetic interference filter incorporating electro-static discharge protection comprising two inductive coils is...
US-9,741,654 Integrated circuit having slot via and method of forming the same
An integrated circuit includes a first conductive line on a first metal level of the integrated circuit. The integrated circuit further includes a second...
US-9,741,653 Devices and methods related to radio-frequency switches having reduced-resistance metal layout
Devices and methods related to radio-frequency (RF) switches having reduced-resistance metal layout. In some embodiments, a field-effect transistor (FET) based...
US-9,741,652 Wiring substrate
A wiring substrate includes a wiring layer on a projection of an insulating layer. The wiring layer includes a first metal layer on an end face of the...
US-9,741,651 Redistribution layer lines
Embodiments herein may relate to a package with a dielectric layer having a first face and a second face opposite the first face. A conductive line of a...
US-9,741,650 Wiring board and semiconductor package
A wiring board includes a wiring layer including a surface on which a recess is formed and a metal layer formed on a bottom surface of the recess. A surface of...
US-9,741,649 Integrated interposer solutions for 2D and 3D IC packaging
An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor...
US-9,741,648 Wiring board
A wiring board includes an insulating substrate having a plurality of laminated insulating layers and a mounting part in one surface of the insulating...
US-9,741,647 Wiring substrate, semiconductor device, and method of manufacturing wiring substrate
A wiring substrate is provided with a first wiring layer including a first land, a first insulative layer formed on the first wiring layer, a second wiring...
US-9,741,646 Package substrate and its fabrication method
This disclosure provides a package substrate and its fabrication method. The package substrate includes: a carrier; a first wiring layer formed on the carrier;...
US-9,741,645 Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures...
Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures and packages are described. For example, a method...
US-9,741,644 Stacking arrangement for integration of multiple integrated circuits
A stacked integrated circuit (IC) system including a substrate, a contour support, and a first and second IC dies. The contour support including a first support...
US-9,741,643 Leadframe strip with vertically offset die attach pads between adjacent vertical leadframe columns
A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad...
US-9,741,642 Semiconductor package with partial plating on contact side surfaces
Embodiments of the present invention are directed to a semiconductor package with partial plating on contact side surfaces. The semiconductor package includes a...
US-9,741,641 Method for manufacturing semiconductor device, and semiconductor device
A semiconductor device, includes a die pad that has a first main surface and a second main surface located on the opposite side of the first main surface; a...
US-9,741,640 Semiconductor device
A light-emitting element according to the present invention includes a semiconductor light-emitting element having a front surface and a rear surface so that...
US-9,741,639 Semiconductor chip, method for producing a semiconductor chip and method for soldering a semiconductor chip to...
A semiconductor chip includes a semiconductor body and a chip metallization applied on the semiconductor body. The chip metallization has an underside facing...
US-9,741,637 Electronic device having a heat dissipation unit and method of manufacturing an electronic device
An embodiment discloses an electronic device, including: a processing component; and a heat dissipation unit thermally coupled to the processing component, the...
US-9,741,636 Nano-thermal agents for enhanced interfacial thermal conductance
A thermal interface material (TIM) using high thermal conductivity nano-particles, particularly ones with large aspect ratios, for enhancing thermal transport...
US-9,741,635 Electronic component
An electronic component includes one or more semiconductor dice embedded in a first dielectric layer, means for a spreading heat in directions substantially...
US-9,741,634 Semiconductor device
A semiconductor device includes: a semiconductor substrate having a main plane; a semiconductor element provided on the main plane of the semiconductor...
US-9,741,633 Semiconductor package including barrier members and method of manufacturing the same
A semiconductor package can include a semiconductor chip on a substrate inside the semiconductor package and an electrode pad spaced apart from the...
US-9,741,632 Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same
A printed circuit module and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned...
US-9,741,631 Substrate storage container with handling members
A handling member includes: a substantially plate-like handling member main body that is arranged along a pair of the side walls, respectively; a circular...
US-9,741,630 Electronic component package and method of manufacturing the same
An electronic component package includes a wiring part including an insulating layer, a conductive pattern formed on the insulating layer, and a conductive via...
US-9,741,629 Plasma processing apparatus and plasma processing method
A plasma processing method of processing layer structure previously formed on an upper surface of a wafer disposed in a processing chamber within a vacuum...
US-9,741,628 Method for manufacturing semiconductor module and intermediate assembly unit of the same
A method for manufacturing a semiconductor module includes the step of soldering two or more semiconductor elements having substrate materials and heights...
US-9,741,627 Substrate etching apparatus and substrate analysis method
The present invention provides an etching apparatus suitable for etching polysilicon on a substrate or bulk silicon constituting the substrate. The present...
US-9,741,626 Vertical transistor with uniform bottom spacer formed by selective oxidation
A method of forming a vertical transistor includes forming at least one fin on stacked layers. The stacked layers include a substrate, a doped silicon layer,...
US-9,741,625 Method of forming a semiconductor device with STI structures on an SOI substrate
In a first aspect, the present disclosure provides a method of forming a semiconductor device, including providing an SOI structure comprising a base substrate,...
US-9,741,624 Spacer shaper formation with conformal dielectric film for void free PMD gap fill
An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer...
US-9,741,623 Dual liner CMOS integration methods for FinFET devices
One illustrative method disclosed herein includes, among other things, performing a first trench etching process to define an upper portion of a first fin for...
US-9,741,622 Methods of forming NMOS and PMOS FinFET devices and the resulting product
One illustrative method disclosed herein includes, among other things, recessing first and second fins to define replacement fin cavities in a layer of...
US-9,741,621 Nano wire structure and method for fabricating the same
A method comprises depositing a sacrificial layer on a first dielectric layer over a substrate, applying a first patterning process, a second patterning...
US-9,741,620 Structures and methods for reliable packages
A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive...
US-9,741,619 Methods for singulating semiconductor wafer
Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of...
US-9,741,618 Methods of forming semiconductor devices
In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within...
US-9,741,617 Encapsulated semiconductor package and method of manufacturing thereof
Encapsulated semiconductor packages and methods of production thereof. As a non-limiting example, a semiconductor package may be produced by partially dicing a...
US-9,741,616 Method for producing optoelectronic semiconductor components, leadframe assembly and optoelectronic...
In one embodiment, the method is configured for producing optoelectronic semiconductor components (1) and includes the steps of: providing a leadframe assembly...
US-9,741,615 Contacts for a fin-type field-effect transistor
Structures for contacting a fin-type field-effect transistor (FinFET) and associated methods. First and second gate structures are formed. The second gate...
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